mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
b8e25ef16a
This patch reads the capabilities register1 and update the host caps accordingly for mmc layer usage. This patch mainly reads for UHS capabilities inorder to support SD3.0. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
434 lines
12 KiB
C
434 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2011, Marvell Semiconductor Inc.
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* Lei Wen <leiwen@marvell.com>
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*
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* Back ported to the 8xx platform (from the 8260 platform) by
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* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
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*/
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#ifndef __SDHCI_HW_H
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#define __SDHCI_HW_H
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#include <asm/io.h>
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#include <mmc.h>
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#include <asm/gpio.h>
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/*
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* Controller registers
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*/
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#define SDHCI_DMA_ADDRESS 0x00
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#define SDHCI_BLOCK_SIZE 0x04
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#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
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#define SDHCI_BLOCK_COUNT 0x06
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#define SDHCI_ARGUMENT 0x08
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#define SDHCI_TRANSFER_MODE 0x0C
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#define SDHCI_TRNS_DMA BIT(0)
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#define SDHCI_TRNS_BLK_CNT_EN BIT(1)
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#define SDHCI_TRNS_ACMD12 BIT(2)
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#define SDHCI_TRNS_READ BIT(4)
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#define SDHCI_TRNS_MULTI BIT(5)
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#define SDHCI_COMMAND 0x0E
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#define SDHCI_CMD_RESP_MASK 0x03
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#define SDHCI_CMD_CRC 0x08
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#define SDHCI_CMD_INDEX 0x10
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#define SDHCI_CMD_DATA 0x20
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#define SDHCI_CMD_ABORTCMD 0xC0
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#define SDHCI_CMD_RESP_NONE 0x00
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#define SDHCI_CMD_RESP_LONG 0x01
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#define SDHCI_CMD_RESP_SHORT 0x02
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#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
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#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
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#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
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#define SDHCI_RESPONSE 0x10
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#define SDHCI_BUFFER 0x20
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#define SDHCI_PRESENT_STATE 0x24
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#define SDHCI_CMD_INHIBIT BIT(0)
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#define SDHCI_DATA_INHIBIT BIT(1)
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#define SDHCI_DOING_WRITE BIT(8)
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#define SDHCI_DOING_READ BIT(9)
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#define SDHCI_SPACE_AVAILABLE BIT(10)
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#define SDHCI_DATA_AVAILABLE BIT(11)
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#define SDHCI_CARD_PRESENT BIT(16)
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#define SDHCI_CARD_STATE_STABLE BIT(17)
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#define SDHCI_CARD_DETECT_PIN_LEVEL BIT(18)
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#define SDHCI_WRITE_PROTECT BIT(19)
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#define SDHCI_HOST_CONTROL 0x28
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#define SDHCI_CTRL_LED BIT(0)
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#define SDHCI_CTRL_4BITBUS BIT(1)
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#define SDHCI_CTRL_HISPD BIT(2)
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#define SDHCI_CTRL_DMA_MASK 0x18
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#define SDHCI_CTRL_SDMA 0x00
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#define SDHCI_CTRL_ADMA1 0x08
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#define SDHCI_CTRL_ADMA32 0x10
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#define SDHCI_CTRL_ADMA64 0x18
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#define SDHCI_CTRL_8BITBUS BIT(5)
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#define SDHCI_CTRL_CD_TEST_INS BIT(6)
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#define SDHCI_CTRL_CD_TEST BIT(7)
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#define SDHCI_POWER_CONTROL 0x29
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#define SDHCI_POWER_ON 0x01
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#define SDHCI_POWER_180 0x0A
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#define SDHCI_POWER_300 0x0C
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#define SDHCI_POWER_330 0x0E
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#define SDHCI_BLOCK_GAP_CONTROL 0x2A
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#define SDHCI_WAKE_UP_CONTROL 0x2B
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#define SDHCI_WAKE_ON_INT BIT(0)
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#define SDHCI_WAKE_ON_INSERT BIT(1)
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#define SDHCI_WAKE_ON_REMOVE BIT(2)
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#define SDHCI_CLOCK_CONTROL 0x2C
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#define SDHCI_DIVIDER_SHIFT 8
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#define SDHCI_DIVIDER_HI_SHIFT 6
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#define SDHCI_DIV_MASK 0xFF
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#define SDHCI_DIV_MASK_LEN 8
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#define SDHCI_DIV_HI_MASK 0x300
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#define SDHCI_PROG_CLOCK_MODE BIT(5)
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#define SDHCI_CLOCK_CARD_EN BIT(2)
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#define SDHCI_CLOCK_INT_STABLE BIT(1)
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#define SDHCI_CLOCK_INT_EN BIT(0)
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#define SDHCI_TIMEOUT_CONTROL 0x2E
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#define SDHCI_SOFTWARE_RESET 0x2F
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#define SDHCI_RESET_ALL 0x01
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#define SDHCI_RESET_CMD 0x02
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#define SDHCI_RESET_DATA 0x04
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#define SDHCI_INT_STATUS 0x30
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#define SDHCI_INT_ENABLE 0x34
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#define SDHCI_SIGNAL_ENABLE 0x38
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#define SDHCI_INT_RESPONSE BIT(0)
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#define SDHCI_INT_DATA_END BIT(1)
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#define SDHCI_INT_DMA_END BIT(3)
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#define SDHCI_INT_SPACE_AVAIL BIT(4)
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#define SDHCI_INT_DATA_AVAIL BIT(5)
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#define SDHCI_INT_CARD_INSERT BIT(6)
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#define SDHCI_INT_CARD_REMOVE BIT(7)
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#define SDHCI_INT_CARD_INT BIT(8)
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#define SDHCI_INT_ERROR BIT(15)
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#define SDHCI_INT_TIMEOUT BIT(16)
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#define SDHCI_INT_CRC BIT(17)
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#define SDHCI_INT_END_BIT BIT(18)
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#define SDHCI_INT_INDEX BIT(19)
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#define SDHCI_INT_DATA_TIMEOUT BIT(20)
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#define SDHCI_INT_DATA_CRC BIT(21)
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#define SDHCI_INT_DATA_END_BIT BIT(22)
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#define SDHCI_INT_BUS_POWER BIT(23)
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#define SDHCI_INT_ACMD12ERR BIT(24)
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#define SDHCI_INT_ADMA_ERROR BIT(25)
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#define SDHCI_INT_NORMAL_MASK 0x00007FFF
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#define SDHCI_INT_ERROR_MASK 0xFFFF8000
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#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
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SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
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#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
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SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
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SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
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SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
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#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
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#define SDHCI_ACMD12_ERR 0x3C
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/* 3E-3F reserved */
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#define SDHCI_CAPABILITIES 0x40
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#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
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#define SDHCI_TIMEOUT_CLK_SHIFT 0
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#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
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#define SDHCI_CLOCK_BASE_MASK 0x00003F00
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#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
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#define SDHCI_CLOCK_BASE_SHIFT 8
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#define SDHCI_MAX_BLOCK_MASK 0x00030000
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#define SDHCI_MAX_BLOCK_SHIFT 16
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#define SDHCI_CAN_DO_8BIT BIT(18)
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#define SDHCI_CAN_DO_ADMA2 BIT(19)
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#define SDHCI_CAN_DO_ADMA1 BIT(20)
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#define SDHCI_CAN_DO_HISPD BIT(21)
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#define SDHCI_CAN_DO_SDMA BIT(22)
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#define SDHCI_CAN_VDD_330 BIT(24)
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#define SDHCI_CAN_VDD_300 BIT(25)
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#define SDHCI_CAN_VDD_180 BIT(26)
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#define SDHCI_CAN_64BIT BIT(28)
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#define SDHCI_CAPABILITIES_1 0x44
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#define SDHCI_SUPPORT_SDR50 0x00000001
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#define SDHCI_SUPPORT_SDR104 0x00000002
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#define SDHCI_SUPPORT_DDR50 0x00000004
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#define SDHCI_USE_SDR50_TUNING 0x00002000
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#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
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#define SDHCI_CLOCK_MUL_SHIFT 16
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#define SDHCI_MAX_CURRENT 0x48
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/* 4C-4F reserved for more max current */
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#define SDHCI_SET_ACMD12_ERROR 0x50
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#define SDHCI_SET_INT_ERROR 0x52
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#define SDHCI_ADMA_ERROR 0x54
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/* 55-57 reserved */
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#define SDHCI_ADMA_ADDRESS 0x58
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/* 60-FB reserved */
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#define SDHCI_SLOT_INT_STATUS 0xFC
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#define SDHCI_HOST_VERSION 0xFE
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#define SDHCI_VENDOR_VER_MASK 0xFF00
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#define SDHCI_VENDOR_VER_SHIFT 8
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#define SDHCI_SPEC_VER_MASK 0x00FF
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#define SDHCI_SPEC_VER_SHIFT 0
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#define SDHCI_SPEC_100 0
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#define SDHCI_SPEC_200 1
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#define SDHCI_SPEC_300 2
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#define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
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/*
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* End of controller registers.
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*/
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#define SDHCI_MAX_DIV_SPEC_200 256
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#define SDHCI_MAX_DIV_SPEC_300 2046
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/*
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* quirks
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*/
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#define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
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#define SDHCI_QUIRK_REG32_RW (1 << 1)
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#define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
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#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
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#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
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/*
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* SDHCI_QUIRK_BROKEN_HISPD_MODE
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* the hardware cannot operate correctly in high-speed mode,
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* this quirk forces the sdhci host-controller to non high-speed mode
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*/
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#define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
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#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
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#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
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#define SDHCI_QUIRK_NO_1_8_V (1 << 9)
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/* to make gcc happy */
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struct sdhci_host;
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/*
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* Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
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*/
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#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
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#define SDHCI_DEFAULT_BOUNDARY_ARG (7)
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struct sdhci_ops {
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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u32 (*read_l)(struct sdhci_host *host, int reg);
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u16 (*read_w)(struct sdhci_host *host, int reg);
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u8 (*read_b)(struct sdhci_host *host, int reg);
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void (*write_l)(struct sdhci_host *host, u32 val, int reg);
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void (*write_w)(struct sdhci_host *host, u16 val, int reg);
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void (*write_b)(struct sdhci_host *host, u8 val, int reg);
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#endif
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int (*get_cd)(struct sdhci_host *host);
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void (*set_control_reg)(struct sdhci_host *host);
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void (*set_ios_post)(struct sdhci_host *host);
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void (*set_clock)(struct sdhci_host *host, u32 div);
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int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
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void (*set_delay)(struct sdhci_host *host);
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};
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struct sdhci_host {
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const char *name;
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void *ioaddr;
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unsigned int quirks;
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unsigned int host_caps;
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unsigned int version;
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unsigned int max_clk; /* Maximum Base Clock frequency */
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unsigned int clk_mul; /* Clock Multiplier value */
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unsigned int clock;
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struct mmc *mmc;
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const struct sdhci_ops *ops;
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int index;
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int bus_width;
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struct gpio_desc pwr_gpio; /* Power GPIO */
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struct gpio_desc cd_gpio; /* Card Detect GPIO */
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uint voltages;
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struct mmc_config cfg;
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};
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#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
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static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
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{
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if (unlikely(host->ops->write_l))
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host->ops->write_l(host, val, reg);
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else
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writel(val, host->ioaddr + reg);
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}
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static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
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{
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if (unlikely(host->ops->write_w))
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host->ops->write_w(host, val, reg);
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else
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writew(val, host->ioaddr + reg);
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}
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static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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if (unlikely(host->ops->write_b))
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host->ops->write_b(host, val, reg);
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else
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writeb(val, host->ioaddr + reg);
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}
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static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
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{
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if (unlikely(host->ops->read_l))
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return host->ops->read_l(host, reg);
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else
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return readl(host->ioaddr + reg);
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}
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static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
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{
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if (unlikely(host->ops->read_w))
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return host->ops->read_w(host, reg);
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else
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return readw(host->ioaddr + reg);
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}
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static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
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{
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if (unlikely(host->ops->read_b))
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return host->ops->read_b(host, reg);
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else
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return readb(host->ioaddr + reg);
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}
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#else
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static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
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{
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writel(val, host->ioaddr + reg);
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}
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static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
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{
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writew(val, host->ioaddr + reg);
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}
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static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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writeb(val, host->ioaddr + reg);
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}
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static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
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{
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return readl(host->ioaddr + reg);
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}
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static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
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{
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return readw(host->ioaddr + reg);
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}
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static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
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{
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return readb(host->ioaddr + reg);
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}
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#endif
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#ifdef CONFIG_BLK
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/**
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* sdhci_setup_cfg() - Set up the configuration for DWMMC
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*
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* This is used to set up an SDHCI device when you are using CONFIG_BLK.
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*
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* This should be called from your MMC driver's probe() method once you have
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* the information required.
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*
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* Generally your driver will have a platform data structure which holds both
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* the configuration (struct mmc_config) and the MMC device info (struct mmc).
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* For example:
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*
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* struct msm_sdhc_plat {
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* struct mmc_config cfg;
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* struct mmc mmc;
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* };
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*
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* ...
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*
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* Inside U_BOOT_DRIVER():
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* .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
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*
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* To access platform data:
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* struct msm_sdhc_plat *plat = dev_get_platdata(dev);
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*
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* See msm_sdhci.c for an example.
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*
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* @cfg: Configuration structure to fill in (generally &plat->mmc)
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* @host: SDHCI host structure
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* @f_max: Maximum supported clock frequency in HZ (0 for default)
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* @f_min: Minimum supported clock frequency in HZ (0 for default)
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*/
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int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
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u32 f_max, u32 f_min);
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/**
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* sdhci_bind() - Set up a new MMC block device
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*
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* This is used to set up an SDHCI block device when you are using CONFIG_BLK.
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* It should be called from your driver's bind() method.
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*
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* See msm_sdhci.c for an example.
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*
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* @dev: Device to set up
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* @mmc: Pointer to mmc structure (normally &plat->mmc)
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* @cfg: Empty configuration structure (generally &plat->cfg). This is
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* normally all zeroes at this point. The only purpose of passing
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* this in is to set mmc->cfg to it.
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* @return 0 if OK, -ve if the block device could not be created
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*/
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int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
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#else
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/**
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* add_sdhci() - Add a new SDHCI interface
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*
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* This is used when you are not using CONFIG_BLK. Convert your driver over!
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*
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* @host: SDHCI host structure
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* @f_max: Maximum supported clock frequency in HZ (0 for default)
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* @f_min: Minimum supported clock frequency in HZ (0 for default)
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* @return 0 if OK, -ve on error
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*/
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int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
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#endif /* !CONFIG_BLK */
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#ifdef CONFIG_DM_MMC
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/* Export the operations to drivers */
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int sdhci_probe(struct udevice *dev);
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extern const struct dm_mmc_ops sdhci_ops;
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#else
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#endif
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#endif /* __SDHCI_HW_H */
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