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2018.03+fslc
u-boot-brain/drivers/ddr/marvell
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Chris Packham 672e559830 ddr: marvell: update ddr controller init and freq 
Update the calculation for tWR and tPD. This improves the DDR refresh
interval and brings the initialization into line with the binary blobs
currently being supplied by Marvell.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2018-01-19 16:30:29 +01:00
..
a38x ddr: marvell: update ddr controller init and freq 2018-01-19 16:30:29 +01:00
axp treewide: remove unneeded semicolons 2017-06-16 10:11:38 -04:00