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https://github.com/brain-hackers/u-boot-brain
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7682a99826
Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
143 lines
3.7 KiB
ArmAsm
143 lines
3.7 KiB
ArmAsm
/*
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modified from SH-IPL+g
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Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
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Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
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Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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#ifdef CONFIG_CPU_SH7751
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#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
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#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
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#ifdef CONFIG_MARUBUN_PCCARD
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#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
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A3:2 A2:15 A1:15 A0:6 A0B:7 */
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#else /* CONFIG_MARUBUN_PCCARD */
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#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
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A3:2 A2:15 A1:15 A0:6 A0B:7 */
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#endif /* CONFIG_MARUBUN_PCCARD */
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#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
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A2: 1-3 A1: 1-3 A0: 0-1 */
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#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
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#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
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#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */
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#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
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#else /* CONFIG_CPU_SH7751 */
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#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
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#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
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#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
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A3:2 A2:15 A1:15 A0:15 A0B:7 */
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#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
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A2: 1-3 A1: 1-3 A0: 0-1 */
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#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
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#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
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#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */
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#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
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#endif /* CONFIG_CPU_SH7751 */
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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write32 CCR_A, CCR_D_DISABLE
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init_bsc:
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write16 FRQCR_A, FRQCR_D
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write32 BCR1_A, BCR1_D
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write16 BCR2_A, BCR2_D
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write32 WCR1_A, WCR1_D
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write32 WCR2_A, WCR2_D
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write32 WCR3_A, WCR3_D
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write32 MCR_A, MCR_D1
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/* Set SDRAM mode */
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write8 SDMR3_A, SDMR3_D
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! Do you need PCMCIA setting?
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! If so, please add the lines here...
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write16 RTCNT_A, RTCNT_D
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write16 RTCOR_A, RTCOR_D
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write16 RTCSR_A, RTCSR_D
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write16 RFCR_A, RFCR_D
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/* Wait DRAM refresh 30 times */
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mov #30, r3
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1:
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mov.w @r1, r0
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extu.w r0, r2
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cmp/hi r3, r2
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bf 1b
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write32 MCR_A, MCR_D2
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/* Set SDRAM mode */
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write8 SDMR3_A, SDMR3_D
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rts
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nop
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.align 2
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CCR_A: .long CCR
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CCR_D_DISABLE: .long 0x0808
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FRQCR_A: .long FRQCR
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FRQCR_D:
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#ifdef CONFIG_CPU_TYPE_R
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.word 0x0e1a /* 12:3:3 */
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#else /* CONFIG_CPU_TYPE_R */
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#ifdef CONFIG_GOOD_SESH4
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.word 0x00e13 /* 6:2:1 */
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#else
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.word 0x00e23 /* 6:1:1 */
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#endif
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.align 2
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#endif /* CONFIG_CPU_TYPE_R */
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BCR1_A: .long BCR1
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BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
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BCR2_A: .long BCR2
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BCR2_D: .long BCR2_D_VALUE /* Bus width settings */
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WCR1_A: .long WCR1
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WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */
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WCR2_A: .long WCR2
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WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
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WCR3_A: .long WCR3
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WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
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RTCSR_A: .long RTCSR
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RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */
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.align 2
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RTCNT_A: .long RTCNT
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RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */
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.align 2
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RTCOR_A: .long RTCOR
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RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */
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.align 2
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SDMR3_A: .long SDMR3_ADDRESS
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SDMR3_D: .long 0x00
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MCR_A: .long MCR
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MCR_D1: .long MCR_D1_VALUE
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MCR_D2: .long MCR_D2_VALUE
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RFCR_A: .long RFCR
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RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */
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.align 2
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