mirror of
https://github.com/brain-hackers/u-boot-brain
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17cb4b8f32
These functions are part of the Linux 4.6 sync. They are being added before the main sync patch in order to make it easier to address the issue across all NAND drivers (many/most of which do not closely track their Linux counterparts) separately from other merge issues. Signed-off-by: Scott Wood <oss@buserror.net>
78 lines
1.6 KiB
C
78 lines
1.6 KiB
C
/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_CMD_NAND)
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#include <nand.h>
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#include <linux/mtd/mtd.h>
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#define SET_CLE 0x10
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#define SET_ALE 0x08
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static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd_to_nand(mtdinfo);
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volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
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if (ctrl & NAND_CTRL_CHANGE) {
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ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
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IO_ADDR_W &= ~(SET_ALE | SET_CLE);
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if (ctrl & NAND_NCE)
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*nCE &= 0xFFFB;
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else
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*nCE |= 0x0004;
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if (ctrl & NAND_CLE)
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IO_ADDR_W |= SET_CLE;
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if (ctrl & NAND_ALE)
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IO_ADDR_W |= SET_ALE;
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this->IO_ADDR_W = (void *)IO_ADDR_W;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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int board_nand_init(struct nand_chip *nand)
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{
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
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clrbits_be32(&fbcs->csmr2, FBCS_CSMR_WP);
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/*
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* set up pin configuration - enabled 2nd output buffer's signals
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* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
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* to use nCE signal
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*/
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clrbits_8(&gpio->par_timer, GPIO_PAR_TIN3_TIN3);
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setbits_8(&gpio->pddr_timer, 0x08);
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setbits_8(&gpio->ppd_timer, 0x08);
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out_8(&gpio->pclrr_timer, 0);
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out_8(&gpio->podr_timer, 0);
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nand->chip_delay = 60;
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nand->ecc.mode = NAND_ECC_SOFT;
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nand->cmd_ctrl = nand_hwcontrol;
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return 0;
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}
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#endif
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