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2018.03+fslc
u-boot-brain/board/altera/arria5-socdk/qts
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Chin Liang See 0db1ac47ee arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1 
Adding new handoff for SDRAM ctrcfg.extratime1 which is
required for stable LPDDR2 operation. Since the board is
using DDR3, the handoff is set to default value 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-27 08:03:08 +02:00
..
iocsr_config.h arm: socfpga: Switch to filtered QTS files 2015-08-23 11:56:20 +02:00
pinmux_config.h arm: socfpga: Make the pinmux table const u8 2015-08-23 11:56:20 +02:00
pll_config.h arm: socfpga: Fix ArriaV SoCDK PLL config 2015-08-23 11:56:21 +02:00
sdram_config.h arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1 2016-10-27 08:03:08 +02:00