// SPDX-License-Identifier: GPL-2.0+ /* * Marvell / Cavium Inc. CN73xx */ /dts-v1/; / { #address-cells = <2>; #size-cells = <2>; soc0: soc@0 { interrupt-parent = <&ciu3>; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; ranges; /* Direct mapping */ ciu3: interrupt-controller@1010000000000 { compatible = "cavium,octeon-7890-ciu3"; interrupt-controller; /* * Interrupts are specified by two parts: * 1) Source number (20 significant bits) * 2) Trigger type: (4 == level, 1 == edge) */ #address-cells = <0>; #interrupt-cells = <2>; reg = <0x10100 0x00000000 0x0 0xb0000000>; }; bootbus: bootbus@1180000000000 { compatible = "cavium,octeon-3860-bootbus","simple-bus"; reg = <0x11800 0x00000000 0x0 0x200>; /* The chip select number and offset */ #address-cells = <2>; /* The size of the chip select region */ #size-cells = <1>; }; gpio: gpio-controller@1070000000800 { #gpio-cells = <2>; compatible = "cavium,octeon-7890-gpio"; reg = <0x10700 0x00000800 0x0 0x100>; gpio-controller; nr-gpios = <32>; /* Interrupts are specified by two parts: * 1) GPIO pin number (0..15) * 2) Triggering (1 - edge rising * 2 - edge falling * 4 - level active high * 8 - level active low) */ interrupt-controller; #interrupt-cells = <2>; /* The GPIO pins connect to 16 consecutive CUI bits */ interrupts = <0x03000 4>, <0x03001 4>, <0x03002 4>, <0x03003 4>, <0x03004 4>, <0x03005 4>, <0x03006 4>, <0x03007 4>, <0x03008 4>, <0x03009 4>, <0x0300a 4>, <0x0300b 4>, <0x0300c 4>, <0x0300d 4>, <0x0300e 4>, <0x0300f 4>; }; reset: reset@1180006001600 { compatible = "mrvl,cn7xxx-rst"; reg = <0x11800 0x06001600 0x0 0x200>; }; uart0: serial@1180000000800 { compatible = "cavium,octeon-3860-uart","ns16550"; reg = <0x11800 0x00000800 0x0 0x400>; clock-frequency = <0>; current-speed = <115200>; reg-shift = <3>; interrupts = <0x08000 4>; }; uart1: serial@1180000000c00 { compatible = "cavium,octeon-3860-uart","ns16550"; reg = <0x11800 0x00000c00 0x0 0x400>; clock-frequency = <0>; current-speed = <115200>; reg-shift = <3>; interrupts = <0x08040 4>; }; }; };