3 Commits

Author	SHA1	Message	Date
Bin Meng	f295e00c61	riscv: Avoid calling sbi_clear_ipi() ... There is no need for S-mode U-Boot to call sbi_clear_ipi() as it can be cleared directly from S-mode. This saves some cycles. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas@auer.io>	2020-03-17 11:29:40 +08:00
Lukas Auer	8b3e97badf	riscv: add functions for reading the IPI status ... Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com>	2019-12-10 08:23:10 +08:00
Lukas Auer	f152febb2a	riscv: implement IPI platform functions using SBI ... The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>	2019-04-08 09:44:26 +08:00