4 Commits

Author	SHA1	Message	Date
Philipp Tomsich	7962a8d5a4	sunxi: add initial clock setup for sun9i for SPL ... This is a cleaned up version set_pll() from Allwinner's boot0 source (bootloader/basic_loader/bsp/bsp_for_a80/common/common.c). [wens@csie.org: Added commit message; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>	2016-10-30 11:38:04 +01:00
Philipp Tomsich	297bb9e0fc	sunxi: DRAM initialisation for sun9i ... This adds DRAM initialisation code for sun9i, which calculates the appropriate timings based on timing information for the supplied DDR3 bin and the clock speeds used. With this DRAM setup, we have verified DDR3 clocks of up to 792MHz (i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration. [wens@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: Chen-Yu Tsai <wens@csie.org> [hdegoede@redhat.com: Drop some huge non-documenting #if 0 ... #endif blocks] [hdegoede@redhat.com: Fix checkpatch warnings] Signed-off-by: Hans de Goede <hdegoede@redhat.com>	2016-10-30 11:38:04 +01:00
Roy Spliet	d0f4200392	sunxi: Match sun4i, sun6i, sun9i CCI definitions for NAND and DMA ... Make sure definitions for NAND clock and DMA gate bits are the same across boards. Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>	2015-05-29 13:46:36 +02:00
Hans de Goede	e35377d726	sun9i: Add clock_sun9i.h with ccu register layout for sun9i ... Add a headerfile with the sun9i ccu register layout. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>	2015-01-22 12:34:55 +01:00