3 Commits

Author	SHA1	Message	Date
Chin Liang See	202936395e	arm: socfpga: sr1500: Adding handoff for SDRAM ctrlcfg.extratime1 ... Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>	2016-10-27 08:03:10 +02:00
Marek Vasut	dbd6fcfbe2	arm: socfpga: Drop the board boilerplate ... Drop all the common board code, since it is not completely useless. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>	2015-12-20 03:36:51 +01:00
Stefan Roese	ae9996c806	arm: socfpga: Add SoCFPGA SR1500 board ... The SR1500 board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices: - SPI NOR - eMMC - Ethernet Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>	2015-12-07 00:15:59 +01:00