Commit Graph

3 Commits

Author SHA1 Message Date
Igor Guryanov
e47d733867 arc: add ECR (exception cause register) output
Exception cause register (ECR) contains value that describes a reason
for exception that has happened. This helps a lot to figure-out what
went wrong.

Now we print this register contents when dumping registers.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
2015-01-15 22:38:42 +03:00
Igor Guryanov
f8cf3d1ebd arc: check caches existence before use
Some cache operations ({i|d}cache_{enable|disable|status} or
flush_dcache_all) are built and used even if CONFIG_SYS_{I|D}CACHE_OFF
is set.

This is required for force disable of caches on early boot.
What if something was executed before U-boot and enabled caches
(low-level bootloaders, previously run kernel etc.)?

But if CPU doesn't really have caches any attempt to access
cache-related AUX registers triggers instruction error exception.

So for convenience we'll try to avoid exceptions by checking if CPU
actually has caches (we check separately data and instruction cache
existence) at all.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
2015-01-15 22:38:42 +03:00
Alexey Brodkin
2f16ac9df4 arc: add cpu files
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Francois Bedard <fbedard@synopsys.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2014-02-07 08:14:32 -05:00