This patch fixes a problem in the Denali (440EPx) SDRAM ECC POST test.
When cache is enabled in the SDRAM area, the values written to SDRAM
need to be flushed from cache to SDRAM using the dcfb instruction.
Without this patch the POST ECC test failed. Now its working again on
platforms with cache enabled in SDRAM.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch moves some ppc4xx related headers from the common include
directory (include/) to the powerpc specific one
(arch/powerpc/include/asm/). This way to common include directory is not
so cluttered with files.
Signed-off-by: Stefan Roese <sr@denx.de>
The ECC POST reported intermittent failures running after power-up on
the Korat PPC440EPx board. Even when the test passed, the debugging
output occasionally reported additional unexpected ECC errors.
This refactoring has three main objectives: (1) minimize the code
executed with ECC enabled during the tests, (2) add more checking of the
results so any unexpected ECC errors would cause the test to fail, and
(3) use synchronization (only) where required by the processor.
Signed-off-by: Larry Johnson <lrj@acm.org>
This patch allows the ECC POST to be used for different boards with the
PPC440 Denali SDRAM controller. Modifications include skipping the test
if ECC is not enabled (as for non-ECC DIMMs) and adding synchronization
to prevent timing errors.
Signed-off-by: Larry Johnson <lrj@acm.org>
