The NanoPi NEO is a simple h3 board with 512MB RAM, ethernet, one usb
and one usb OTG connector.
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Update the README to add support for K2G EVM. Also
- Add steps on how to use MMC boot
- Fix load address when using CCS
- Update build target to u-boot.bin from u-boot-dtb.bin as all ks2
platforms uses DT.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
When beagleboard-X15 is booted, we see the following log:
Unidentified board claims BBRDX15_ in eeprom header
This is because of the missing check for x15 (the default) and reports
an error for a valid board configuration. Fix the same.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Felipe Balbi has move on from TI and the current email ID is no longer
valid. So, replacing with Lokesh.
While at it, update missing config file which was untracked.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
We are supposed to not add config entries with only "default y"
in board/SoC Kconfig files.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Add ARCH_SUPPORT_PSCI as a non-configurable option that platforms
can select. Then, move CONFIG_ARMV7_PSCI, which is automatically
enabled if both ARMV7_NONSEC and ARCH_SUPPORT_PSCI are enabled.
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The PBIAS fixing is done in the MMC driver, and doing it in the
the board file conflicts with the driver causing intermittent
hangs on reboot. Remove this from the board file and let
the driver do it.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Remove the device definition from board file, update the driver with
the new compatible property and update config with necessary options.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
On the raspberry pi, you can disable the serial port to gain dynamic frequency
scaling which can get handy at times.
However, in such a configuration the serial controller gets its rx queue filled
up with zero bytes which then happily get transmitted on to whoever calls
getc() today.
This patch adds detection logic for that case by checking whether the RX pin is
mapped to GPIO15 and disables the mini uart if it is not mapped properly.
That way we can leave the driver enabled in the tree and can determine during
runtime whether serial is usable or not, having a single binary that allows for
uart and non-uart operation.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
warp7 has two targets:
- warp7_defconfig: boots in non-secure mode
- warp7_secure_defconfig: boots in secure mode
Print the mode that is being used to help users to easily identify
which target is running on the board.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
To be in the safe side we need to enable the CCGR clocks prior
to calling arch_cpu_init().
Inspired by Tim Harvey's commit d783c2744f ("imx: ventana: fix boot to SD").
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Tested-by: Eric Nelson <eric@nelint.com>
Adjust DDR3 initialization done in SPL by comparing them against
the NXP DCD table.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk,
we observe a hang when going into the lowest operational point of cpufreq.
This hang issue does not happen on the NXP U-Boot version.
After comparing the SPL DDR initialization against the DCD table
from NXP U-Boot, the key difference that causes the hang is the
MDREF register setting:
DATA 4 0x021B0020 0x00000800
,which means:
REF_SEL = 0 --> Periodic refresh cycle: 64kHz
REFR = 1 ---> Refresh Rate - 2 refreshes
So adjust the MDREF initialization for mx6ul_evk accordingly
to fix the kernel hang issue at low bus frequency.
Reported-by: Eric Nelson <eric@nelint.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.
Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:
$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800
So introduce a mechanism for users to be able to configure
REFSEL and REFR fields as needed.
Keep all the mx6 SPL users in their current REF_SEL and REFR values,
so no functional changes for the existing users.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Register LDOGCTL contains only bit 0 as a valid bit, so there is no need
to do a read-modify-write operation.
Simplify the code by writing directly to this register.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Register LDOGCTL contains only bit 0 as a valid bit, so there is no need
to do a read-modify-write operation.
Simplify the code by writing directly to this register.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Register LDOGCTL contains only bit 0 as a valid bit, so there is no need
to do a read-modify-write operation.
Simplify the code by writing directly to this register.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
ft_board_setup may return early in the case that the board revision
cannot be obtained. In that case it is assumed that no revision
specific correction in the fdt is neccessary. But the mtd partitions
will not be fixed up either altough they are not revision specific.
Move the call to fdt_fixup_mtdparts in front of the revision specific
part to ensure that the partitions are fixed up even if the board
revision cannot be obtained.
While on it, fix a spelling mistake in a comment introduced by the
same commit.
Fixes: 62d6bac660 ("ARM: board: cm_fx6: fixup mtd partitions in the fdt")
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Nikita Kiryanov <nikita@compulab.co.il>
Only a single pad is changed to change sdhc2_dat3 from an
SDIO pin to and from GPIO4:5, so remove the array and use
the imx_iomux_v3_setup_pad() routine.
Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Since commit a13d3757f7 ("warp: Use imx_ddr_size() for calculating the
DDR size") warp board no longer boots.
The reason for the breakage is that the warp board is using the DDR
configuration from mx6slevk. A fundamental difference between warp and
mx6slevk is that warp only uses one DDR chip select while mx6slevk uses two.
The imx_ddr() function calculates the RAM size in runtime by reading the
values of registers MDCTL and MDMISC.
So in order to fix this warp boot issue, create a imximage DDR file specific
to warp, where the MDCTL register is configured to only activates a single
chip select.
Reported-by: Breno Lima <breno.lima@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Breno Lima <breno.lima@nxp.com>
Add support for Advantech DMS-BA16 board. The board is based on Advantech
BA16 module which has a i.MX6D processor. The board supports:
- FEC Ethernet
- USB Ports
- SDHC and MMC boot
- SPI NOR
- LVDS and HDMI display
Basic information about the module:
- Module manufacturer: Advantech
- CPU: Freescale ARM Cortex-A9 i.MX6D
- SPECS:
Up to 2GB Onboard DDR3 Memory;
Up to 16GB Onboard eMMC NAND Flash
Supports OpenGL ES 2.0 and OpenVG 1.1
HDMI, 24-bit LVDS
1x UART, 2x I2C, 8x GPIO,
4x Host USB 2.0 port, 1x USB OTG port,
1x micro SD (SDHC),1x SDIO, 1x SATA II,
1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: u-boot@lists.denx.de
Cc: sbabic@denx.de
mx7dsabresd has two targets:
- mx7dsabresd_defconfig: boots in non-secure mode
- mx7dsabresd_secure_defconfig: boots in secure mode
Print the mode that is being used to help users to easily identify
which target is running on the board.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Casting "int"s to pointers is only valid for 32-bit systems.
Add the appropriate pointer type cast to avoid a compiler warning
when compiling for AArch64.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
There is no "CONFIG_MACH_SUN50I_A64" in upstream U-Boot, so fix
the name to prevent the option to be enabled.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Orange Pi Plus2E is an extended version of the Orange Pi Pc Plus,
with 2G RAM and an external gbit ethernet phy.
The dts file is identical to the one submitted to the upstream kernel,
except that it has the pending patch to enable the ethernet controller
squashed in, as u-boot already has sun8i-emac support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
A33-OLinuXino is A33 development board designed by Olimex LTD.
It has AXP223 PMU, 1GB DRAM, a micro SD card, one USB-OTG connector,
headphone and mic jacks, connector for LiPo battery and optional
4GB NAND Flash.
It has two 40-pin headers. One for LCD panel, and one for
additional modules. Also there is CSI/DSI connector.
The dts files are identical to the ones submitted to the upstream kernel.
Signed-off-by: Stefan Mavrodiev <stefan.mavrodiev@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The iNet D978 rev2 is a tablet board designed by iNet, which is intended to
use on 10" tablets with a appearance like Apple iPad. It has A33 SoC, 1GB
RAM, 8GB/16GB NAND, SDIO Wi-Fi, a MicroUSB port and a MicroSD slot.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Colorado TK1 SOM is a small form factor board similar to the
Jetson TK1. The main differences lie in the pinmux, and in that the
PCIe controller is set to use in 4lanes+1lane, rather than 2+2.
The pinmux header here was generated from a spreadsheet provided by
Colorado Engineering using the tegra-pinmux scripts. The spreadsheet
was converted from v09 to v11 by me.
Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This introduces two board defconfig files for generating EFI 32-bit
and 64-bit payloads, to run on QEMU x86 target.
With these in place, hopefully buildman will catch any build error
with EFI payload support on x86.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch add maintainer information for rk3399 evb.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
