Commit Graph

186 Commits

Author SHA1 Message Date
Masahiro Yamada
dffb86e468 of: flip CONFIG_SPL_DISABLE_OF_CONTROL into CONFIG_SPL_OF_CONTROL
As we discussed a couple of times, negative CONFIG options make our
life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ...
and here is another one.

Now, there are three boards enabling OF_CONTROL on SPL:
 - socfpga_arria5_defconfig
 - socfpga_cyclone5_defconfig
 - socfpga_socrates_defconfig

This commit adds CONFIG_SPL_OF_CONTROL for them and deletes
CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert
the logic.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-08-18 13:46:04 -04:00
Masahiro Yamada
cc7aebe819 fdtdec: fix OF_CONTROL switch
There is no case where defined(SPL_DISABLE_OF_CONTROL) is true.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-08-18 13:46:04 -04:00
Andrew Bradford
f3b84a3032 x86: baytrail: Configure FSP UPD from device tree
Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.

Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay
Fixed lines >80col
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-14 03:24:21 -06:00
Marek Vasut
6ab00db226 arm: socfpga: misc: Reset ethernet from OF
Reset the GMAC ethernets based on the "resets" OF node instead of ad-hoc
hardcoded values in the U-Boot code. Since we don't have a proper reset
framework in place yet, we have to do this slightly ad-hoc parsing of the
OF tree instead.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2015-08-08 14:14:08 +02:00
York Sun
28445aa7ec lib/fdtdec: Fix fdt_addr_t and fdt_size_t typedef
fdt_addr_t is a physical address. It can be either 64-bit or 32-bit,
depending on the architecture. It should be phys_addr_t instead of
u64 or u32. Similarly, fdt_size_t is changed to phys_size_t.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Simon Glass <sjg@chromium.org>
2015-08-06 07:31:36 -06:00
Simon Glass
5ae3a5e887 dts: Drop unused compatible ID for the NXP video bridge
This has moved to driver model so we can drop the fdtdec support.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:17 -06:00
Simon Glass
68964dbc83 video: Remove the old parade driver
We have a new one which uses driver model and device tree configuration.
Remove the old one.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:16 -06:00
Simon Glass
05bccbcd76 power: Remove old TPS65090 drivers
Remove the old drivers (both the normal one and the cros_ec one) now that
we have new drivers that use driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-05 21:06:16 -06:00
Tom Warren
7aaa5a60ce ARM: Tegra210: Add support to common Tegra source/config files
Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too. This also adds misc 64-bit changes
from Thierry Reding/Stephen Warren.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2015-07-28 10:30:20 -07:00
Simon Glass
257bfd2e21 dm: usb: tegra: Drop legacy USB code
Drop the code that doesn't use driver model for USB.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-10 19:26:55 -06:00
Simon Glass
af28224546 sandbox: Move CONFIG_SANDBOX_SERIAL to Kconfig
Move this over to Kconfig and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-06-10 19:26:55 -06:00
Gabriel Huau
5318f18d2c x86: gpio: add pinctrl support from the device tree
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.

Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:32:08 -06:00
Bin Meng
9c7dea602e x86: Refactor PIRQ routing support
PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 02:39:39 -06:00
Simon Glass
00f3732752 tegra: video: Support serial output resource (SOR) on tegra124
The SOR is required for talking to eDP LCD panels. Add a driver for this
which will be used by the DisplayPort driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:11 -07:00
Simon Glass
12e671142d fdt: Add binding decode function for display-timings
This is useful for display parameters. Add a simple decode function to read
from this device tree node.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-05-13 09:24:06 -07:00
Simon Glass
f56da290b8 dm: usb: exynos: Drop legacy USB code
Drop the code that doesn't use driver model for USB.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-05-06 14:00:35 -06:00
Simon Glass
b2b0d3e712 dm: core: Select device tree control correctly for SPL
Some boards will not use device tree for SPL even with driver model. Add
the logic to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-23 09:05:54 -06:00
Simon Glass
0879361fd3 fdt: Rename setup_fdt() and make it prepare also
There is little reason to split these two functions. Bring them together
which simplifies the init sequence.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-23 09:05:53 -06:00
Simon Glass
b45122fdf5 fdt: sandbox: Move setup code from board_f to fdtdec
We want to be able to set up the device tree in SPL, so move this code
to a common place.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-23 09:05:53 -06:00
Simon Glass
3fbb78711c cros_ec: exynos: Match up device tree with kernel version
The U-Boot device trees are slightly different in a few places. Adjust them
to remove most of the differences. Note that U-Boot does not support the
concept of interrupts as distinct from GPIOs, so this difference remains.

For sandbox, use the same keyboard file as for ARM boards and drop the
host emulation bus which seems redundant.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:16 -06:00
Simon Glass
ce6adaa4b5 fdt: Drop LPC compatible string in fdtdec
This is not needed now that we have moved chromebook_link and cros_ec to
driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:16 -06:00
Simon Glass
672055e20b fdt: cros_ec: Drop compatible string in fdtdec
This is not needed now that we have moved to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:16 -06:00
Simon Glass
90b16d1491 x86: chromebook_link: dts: Add PCH and LPC devices
The PCH (Platform Controller Hub) is on the PCI bus, so show it as such.
The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the
right place also.

Rename the compatible strings to be more descriptive since this board is the
only user. Once we are using driver model fully on x86, these will be
dropped.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:15 -06:00
Simon Glass
106cce9604 fdt: Tighten up error handling in fdtdec_get_pci_addr()
This function returns -ENOENT when the property is missing (which the caller
might forgive) and also when the property is present but incorrectly
formatted (which many callers would like to report).

Update the error return value to allow these different situations to be
distinguished.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-16 19:27:42 -06:00
Simon Glass
5f7bfdd630 fdt: Export fdtdec_get_number() for general use
This function is missing a prototype but is more widey useful. Add it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-04-16 19:27:41 -06:00
Bin Meng
0eb9dc76e2 fdtdec: Improve fdtdec_get_pci_bdf() documentation
Add the description that how the compatible property is involved in
the fdtdec_get_pci_bdf() documentation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-03-24 21:22:37 -06:00
Masahiro Yamada
6462cdedc2 ARM: UniPhier: adjust device trees for business transfer
Panasonic's System LSI products, UniPhier SoC family, have been
transferred to Socionext Inc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-03-15 13:37:00 +09:00
Masahiro Yamada
1e7df7c4e4 usb: UniPhier: add UniPhier on-chip xHCI host driver support
Support xHCI host driver used on Panasonic UniPhier platform.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Marek Vasut <marex@denx.de>
2015-03-01 00:03:00 +09:00
Bin Meng
c89ada017f fdtdec: Add compatible id and string for Intel Quark MRC
Add COMPAT_INTEL_QRK_MRC and "intel,quark-mrc" so that fdtdec can
decode Intel Quark MRC node.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-02-06 12:07:43 -07:00
Simon Glass
b9749eb5e4 dm: exynos: Drop unused COMPAT features for SPI
This has moved to driver model so we don't need the fdtdec support.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2015-01-29 17:09:57 -07:00
Simon Glass
dedff1a000 dm: tegra: Drop unused COMPAT features for I2C, SPI
These have moved to driver model so we don't need the fdtdec support.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:56 -07:00
Simon Glass
009067c3b7 dm: fdt: Remove the old GPIO functions
Now that we support device tree GPIO bindings directly in the driver model
GPIO uclass we can remove these functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:53 -07:00
Simon Glass
57068a7aeb dm: fdt: Add a function to decode phandles with arguments
For GPIOs and other functions we want to look up a phandle and then decode
a list of arguments for that phandle. Each phandle can have a different
number of arguments, specified by a property in the target node. This is
the "#gpio-cells" property for GPIOs.

Add a function to provide this feature, taken modified from Linux 3.18.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-29 17:09:50 -07:00
Simon Glass
5da38086bd x86: dts: Add compatible string for Intel ICH9 SPI controller
Add this to the enum so that we can use the various fdtdec functions. A
later commit will move this driver to driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-23 21:44:59 -07:00
Bin Meng
a62e84d7b1 fdt: Add several apis to decode pci device node
This commit adds several APIs to decode PCI device node according to
the Open Firmware PCI bus bindings, including:
- fdtdec_get_pci_addr() for encoded pci address
- fdtdec_get_pci_vendev() for vendor id and device id
- fdtdec_get_pci_bdf() for pci device bdf triplet
- fdtdec_get_pci_bar32() for pci device register bar

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Include <pci.h> in fdtdec.h and adjust tegra to fix build error)
2015-01-13 07:24:40 -08:00
Thierry Reding
f315828b0d pci: tegra: Add Tegra PCIe driver
Add support for the PCIe controller found on some generations of Tegra.
Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has 3 root
ports with a total of 6 lanes and Tegra124 has 2 root ports with a total
of 5 lanes.

This is based on the Linux kernel driver, originally submitted upstream
by Mike Rapoport.

Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
79c7a90f6c ARM: tegra: Implement XUSB pad controller
This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
with weak symbols on Tegra114.

Tegra20 and Tegra30 also provide weak symbols for these functions so
that drivers can use the same API irrespective of which SoC they're
being built for.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
6173c45b21 power: Add AMS AS3722 PMIC support
The AS3722 provides a number of DC/DC converters and LDOs as well as 8
GPIOs.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Tom Rini
88342103cc Merge git://git.denx.de/u-boot-fdt 2014-12-01 15:24:26 -05:00
Tom Rini
f4e7e2d121 Merge git://git.denx.de/u-boot-x86 2014-12-01 15:24:07 -05:00
Masahiro Yamada
0bd4e39d2b fdt: remove fdtdec_get_alias_node() function
The fdt_path_offset() checks an alias too.

fdtdec_get_alias_node(blob, "foo") is equivalent to
fdt_path_offset(blob, "foo").

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-11-27 09:12:30 -07:00
Tom Rini
1fc4e6f486 Merge git://git.denx.de/u-boot-fdt 2014-11-26 11:21:14 -05:00
Simon Glass
effcf067df x86: Add initial video device init for Intel GMA
Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range
of video devices. Add code to set up the hardware on ivybridge. Part of the
init happens in native code, part of it happens in a 16-bit option ROM for
those nostalgic for the 1970s.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:16 -07:00
Simon Glass
bb80be3916 x86: Add init for model 206AX CPU
Add the setup code for the CPU so that it can be used at full speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
3ac839352d x86: ivybridge: Add SATA init
Add code to set up the SATA interfaces on boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
65dd74a674 x86: ivybridge: Implement SDRAM init
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree. This
also needs the Intel Management Engine (me.bin) to work. Binary blobs
everywhere: so far we have MRC, ME and microcode.

SDRAM init works by setting up various parameters and calling the MRC. This
in turn does some sort of magic to work out how much memory there is and
the timing parameters to use. It also sets up the DRAM controllers. When
the MRC returns, we use the information it provides to map out the
available memory in U-Boot.

U-Boot normally moves itself to the top of RAM. On x86 the RAM is not
generally contiguous, and anyway some RAM may be above 4GB which doesn't
work in 32-bit mode. So we relocate to the top of the largest block of
RAM we can find below 4GB. Memory above 4GB is accessible with special
functions (see physmem).

It would be possible to build U-Boot in 64-bit mode but this wouldn't
necessarily provide any more memory, since the largest block is often below
4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large
ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit
kernels directly so this does not pose a limitation in that area. Also there
are probably parts of U-Boot that will not work correctly in 64-bit mode.
The MRC is one.

There is some work remaining in this area. Since memory init is very slow
(over 500ms) it is possible to save the parameters in SPI flash to speed it
up next time. Suspend/resume support is not fully implemented, or at least
it is not efficient.

With this patch, link boots to a prompt.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
77f9b1fb62 x86: ivybridge: Perform Intel microcode update on boot
Microcode updates are stored in the device tree. Work through these and
apply any that are needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
a9f04d49e5 fdt: Add a function to decode a variable-sized u32 array
Sometimes an array can be of variable size up to a maximum. Add a helper
function to decode this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:24:11 +01:00
Simon Glass
2640387148 fdt: Add a function to decode a named memory region
Permit decoding of a named memory region from the device tree. This allows
easy run-time configuration of the address of on-chip SRAM, SDRAM, etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
2014-11-21 04:43:18 +01:00
Simon Glass
f3cc44f984 fdt: Enhance flashmap function to deal with region properties
Flash regions can optionally be compressed or hashed. Add the ability to
read this information from the flashmap.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Tom Rini <trini@ti.com>
2014-11-21 04:43:17 +01:00
Simon Glass
76489832b2 fdt: Use the correct return types for fdtdec_decode_region()
Use the correct FDT data types for this function. Also add more debugging.

Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
2014-11-21 04:43:17 +01:00
Tom Rini
dee8abcd80 Merge git://git.denx.de/u-boot-x86 2014-10-23 06:54:03 -04:00
Simon Glass
ca42d3f7ee x86: dts: Add device tree compatible string for Intel IPC
Add this to the table so that it can be recognised.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-10-22 21:50:32 -06:00
Thierry Reding
9f85eee72a fdt: Add a function to return PCI BDF triplet
The fdtdec_pci_get_bdf() function returns the bus, device, function
triplet of a PCI device by parsing the "reg" property according to the
PCI device tree binding.

Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-10-22 16:56:41 -06:00
Thierry Reding
56f42242f0 fdt: Add resource parsing functions
Add the fdt_get_resource() and fdt_get_named_resource() functions which
can be used to parse resources (memory regions) from an FDT. A helper to
compute the size of a region is also provided.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-10-22 16:56:41 -06:00
Tom Rini
8d028d404f Merge branch 'master' of git://git.denx.de/u-boot-dm 2014-09-13 16:32:52 -04:00
Simon Glass
aac07d49d0 dm: fdt: Add a function to look up a chosen node
Within /chosen we may have a node which points to another node, similar
to how /aliases works. Add a helper function to do this lookup.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-10 12:59:59 -06:00
Vadim Bendebury
9e8f664ecb video: Add driver for Parade PS8625 dP to LVDS bridge
The initialization table comes from the "Illustration of I2C command
for initialing PS8625" document supplied by Parade.

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Ajay Kumar
45c480c9f6 video: exynos_fimd: Add framework to disable FIMD sysmmu
On Exynos5420 and newer versions, the FIMD sysmmus are in
"on state" by default.
We have to disable them in order to make FIMD DMA work.
This patch adds the required framework to exynos_fimd driver,
and disables FIMD sysmmu on Exynos5420.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05 20:37:07 +09:00
Simon Glass
3234aa4bab fdt: Add a function to get the node offset of an alias
This simple function returns the node offset of a named alias.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:26 +01:00
Simon Glass
5c33c9fdbb fdt: Add a function to get the alias sequence of a node
Aliases are used to provide U-Boot's numbering of devices, such as:

aliases {
	spi0 = "/spi@12330000";
}

spi@12330000 {
	...
}

This tells us that the SPI controller at 12330000 is considered to be the
first SPI controller (SPI 0). So we have a numbering for the SPI node.

Add a function that returns the numbering for a node assume that it exists
in the list of aliases.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-23 14:07:25 +01:00
Simon Glass
a9cf6da925 exynos: Enable the LCD backlight for snow
The backlight uses FETs on the TPS65090. Enable this so that the display
is visible.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-28 10:58:19 +09:00
Tom Wai-Hong Tam
ac1058fdb7 power: Add support for TPS65090 PMU chip.
This adds driver support for the TPS65090 PMU. Support includes
hooking into the pmic infrastructure  so that the pmic commands
can be used on the console. The TPS65090 supports the following
functionality:

- fet enable/disable/querying
- getting and setting of charge state

Even though it is connected to the pmic infrastructure it does
not hook into the pmic charging charging infrastructure.

The device tree binding is from Linux, but only a small subset of
functionality is supported.

Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Katie Roberts-Hoffman <katierh@chromium.org>
Signed-off-by: Rong Chang <rongchang@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-28 10:58:19 +09:00
Jaehoon Chung
7d3ca0f89d ARM: dts: exynos: rename from EXYNOS5_DWMMC to EXYNOS_DWMMC
Exynos serise can be supported the dw-mmc controller.
So, it's good that used the general prefix as "_EXYNOS_DWMMC".

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-05-16 14:54:26 +09:00
Albert ARIBAUD
ab6423cae0 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Trivial merge conflict, needed to manually remove
local_info as per commit 41364f0f.

Conflicts:
	board/samsung/common/board.c
2014-03-25 10:53:15 +01:00
Simon Glass
7d95f2a329 sandbox: Add LCD driver
Add a simple LCD driver which uses SDL to display the image. We update the
image regularly, while still providing for reasonable performance.

Adjust the common lcd code to support sandbox.

For command-line runs we do not want the LCD to be displayed, so add a
--show_lcd option to enable it.

Tested-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:49 -06:00
Simon Glass
df93d90aea cros_ec: sandbox: Add Chrome OS EC emulation
Add a simple emulation of the Chrome OS EC for sandbox, so that it can
perform various EC tasks such as keyboard handling.

Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:47 -06:00
Simon Glass
006e73b9ca cros_ec: Add a function for reading a flash map entry
A flash map describes the layout of flash memory in terms of offsets and
sizes for each region. Add a function to read a flash map entry from the
device tree.

Reviewed-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-03-17 20:05:46 -06:00
Piotr Wilczek
3577fe8be9 drivers:mmc:sdhci: enable support for DT
This patch enables support for device tree for sdhci driver.
Non DT case is still supported.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-03-12 19:54:59 +09:00
Piotr Wilczek
de461c526e video:mipidsim:fdt: Add DT support for mipi dsim driver
This patch enables parsing mipi data from device tree.
Non device tree case is still supported.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-03-12 19:54:59 +09:00
Stephen Warren
a73ca4789f mmc: tegra: support Tegra124
Tegra124's MMC controller is very similar to earlier SoC generations,
and can be supported by the same driver.

However, there are some non-backwards-compatible HW differences, and
hence a new DT compatible value must be used to describe the HW. This
patch updates the driver to support that new compatible value.

That said, the HW differences are only relevant when enabling certain
high-performance transfer modes. Since the driver is currently very
simple and doesn't enable those modes, we don't actually need to address
any of these HW differences in the code yet, hence the simple nature of
this patch.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-02-03 09:46:45 -07:00
Vivek Gautam
108b85be25 exynos5: dts: Add COMPAT string data for USB 3.0 PHY and XHCI
Adding required compatible string for xHCI host controller
as well as USB 3.0 PHY to enable dt support for usb 3.0 on
exynos5.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>
2013-10-20 23:42:38 +02:00
Tom Rini
c2120fbfbc Merge branch 'master' of git://git.denx.de/u-boot-i2c
The sandburst-specific i2c drivers have been deleted, conflict was just
over the SPDX conversion.

Conflicts:
	board/sandburst/common/ppc440gx_i2c.c
	board/sandburst/common/ppc440gx_i2c.h

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:50:24 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
naveen krishna chatradhi
ecbd7e1ec7 fdtdec: Add compatible string for High speed i2c
Adds a new COMPAT string exynos5-hsi2c for high speed i2c controller
available on exynos5 SoCs from Samsung.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
2013-07-23 08:34:58 +02:00
Tom Rini
fbbbc86e8e Merge branch 'master' of git://git.denx.de/u-boot-arm
Fix a trivial conflict in arch/arm/dts/exynos5250.dtsi about gpio and
serial.

Conflicts:
	arch/arm/dts/exynos5250.dtsi

Signed-off-by: Tom Rini <trini@ti.com>
2013-07-12 10:36:48 -04:00
Jim Lin
7e44d9320e ARM: Tegra: USB: EHCI: Add support for Tegra30/Tegra114
Tegra30 and Tegra114 are compatible except PLL parameters.

Tested on Tegra30 Cardhu, and Tegra114 Dalmore
platforms. All works well.

Signed-off-by: Jim Lin <jilin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-07-11 14:15:15 -07:00
Hung-ying Tyan
713cb68045 cros: adds cros_ec keyboard driver
This patch adds the driver for keyboard that's controlled by ChromeOS EC.

Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2013-06-26 10:13:31 -04:00
Hung-ying Tyan
88364387c6 cros: add cros_ec driver
This patch adds the cros_ec driver that implements the protocol for
communicating with Google's ChromeOS embedded controller.

Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2013-06-26 10:07:11 -04:00
Rajeshwari Shinde
ee1e3c2f23 EXYNOS5: FDT: Add compatible strings for Serial
Add required compatible information for s5p serial driver

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-24 20:47:41 +09:00
Tom Rini
348e47f766 Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-06-22 07:38:12 -04:00
Amar
45a4d4d35a FDT: Add compatible string for DWMMC
Add required compatible information for DWMMC driver.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Amar <amarendra.xt@samsung.com>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-06-13 17:35:13 +09:00
Vincent Palatin
ec34fa5e43 tpm: Add support for new Infineon I2C TPM (SLB 9645 TT 1.2 I2C)
Add support for Infineon's new SLB 9645 TT 1.2 I2C TPMs,
which supports clockstretching, combined reads and a bus speed of
up to 400khz. The device also has a new device id.

This is based on the kernel patch provided by Infineon :
https://gerrit.chromium.org/gerrit/42332

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Tom Wai-Hong Tam <waihong@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
2013-06-03 01:26:25 -07:00
Tom Rini
17059f972f Merge branch 'master' of git://git.denx.de/u-boot-arm 2013-04-15 07:46:11 -04:00
Rong Chang
f626799816 tpm: Add Infineon slb9635_i2c TPM driver
Add a driver for the I2C TPM from Infineon.

Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rong Chang <rongchang@chromium.org>
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-04-12 14:13:00 -07:00
Albert ARIBAUD
fed029f3c3 Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2013-04-04 15:44:57 +02:00
Albert ARIBAUD
009d75ccc1 Merge branch 'u-boot/master' into 'u-boot-arm/master'
Conflicts:
	drivers/spi/tegra20_sflash.c
	include/fdtdec.h
	lib/fdtdec.c
2013-03-28 18:50:01 +01:00
Ajay Kumar
1e4706a715 EXYNOS5: FDT: Add compatible strings for FIMD
Add required compatible information for FIMD.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-27 21:23:11 +09:00
Ajay Kumar
d7377b5193 EXYNOS: FDT: Add compatible strings for FIMD
Add required compatible information for FIMD.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-27 21:17:23 +09:00
Albert ARIBAUD
ebd749da69 Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master' 2013-03-26 10:40:13 +01:00
Albert ARIBAUD
412665b461 Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' 2013-03-26 09:51:09 +01:00
Allen Martin
c3bb3c8bb3 tegra114: fdt: add compatible string for tegra114 SPI ctrl
Add "nvidia,tegra114-spi" to represent t114 SPI controller hardware.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-25 09:56:06 -07:00
Simon Glass
bb8215f437 sf: Enable FDT-based configuration and memory mapping
Enable device tree control of SPI flash, and use this to implement
memory-mapped SPI flash, which is supported on Intel chips.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:37 -07:00
Simon Glass
4397a2a80b fdt: Add fdtdec_get_addr_size() to read reg properties
It is common to have a "reg = <address size>" property in the FDT.
Add a function to handle this, similar to the existing
fdtdec_get_addr();

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-19 08:45:36 -07:00
Tom Warren
f4e4e0b0e3 Tegra30: mmc: Add Tegra30 SDMMC compatible entry to fdtdec & driver
Tegra30 SD/MMC controller differs enough from Tegra20 that it
needs its own entry in the compat_names/compat_id tables and in
the Tegra MMC driver.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:44 -07:00
Tom Warren
c9aa831ee2 Tegra: MMC: Add DT support to MMC driver for all T20 boards
tegra_mmc_init() now parses the DT info for bus width, WP/CD GPIOs, etc.
Tested on Seaboard, fully functional.

Tamonten boards (medcom-wide, plutux, and tec) use a different/new
dtsi file w/common settings.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14 11:06:42 -07:00
Tom Warren
e32624ef82 Tegra: I2C: Add T114 clock support to tegra_i2c driver
T114 has a slightly different I2C clock, with a new (extra) divisor
in standard/fast mode and HS mode. Tested on my Dalmore, and the I2C
clock is 100KHz +/- 3Hz on my Saleae Logic analyzer.

Added a new entry in compat_names for T114 I2C since it differs
from the previous Tegra SoCs. A flag is set when T114 I2C HW is
found so new features like the extra clock divisor can be used.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
2013-03-14 11:06:41 -07:00
Akshay Saraswat
618766c098 Exynos5: FDT: Add TMU device node values
Fdt entry for Exynos TMU driver specific pre-defined values used for
calibration of current temperature and defining threshold values.

Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-12 17:06:06 +09:00
Rajeshwari Shinde
7772bb787e EXYNOS5: FDT: Add compatible strings for MAX98095
Add required compatible information for MAX98095 codec

Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-08 22:34:19 +09:00
Allen Martin
b19f57491a tegra: add SPI SLINK driver
Add driver for tegra SPI "SLINK" style driver.  This controller is
similar to the tegra20 SPI "SFLASH" controller.  The difference is
that the SLINK controller is a genernal purpose SPI controller and the
SFLASH controller is special purpose and can only talk to FLASH
devices.  In addition there are potentially many instances of an SLINK
controller on tegra and only a single instance of SFLASH.  Tegra20 is
currently ths only version of tegra that instantiates an SFLASH
controller.

This driver supports basic PIO mode of operation and is configurable
(CONFIG_OF_CONTROL) to be driven off devicetree bindings.  Up to 4
devices per controller may be attached, although typically only a
single chip select line is exposed from tegra per controller so in
reality this is usually limited to 1.

To enable this driver, use CONFIG_TEGRA_SLINK

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11 10:35:25 -07:00