SPI Flash (M25P40) is connected to the SPI1 bus, we need a few
qe_iop entries to actually enable SPI1 on these boards.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch sets memory window for Serial RapidIO on MPC8569E-MDS
boards.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Simply add some defines, and adjust TLBe setup to include some
space for eLBC NAND.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2
(in 1-bit mode). When eSDHC is used, we should switch u-boot console to
UART1, and make the proper device-tree fixups.
Because of an erratum in prototype boards it is impossible to use eSDHC
without disabling UART0 (which makes it quite easy to 'brick' the board
by simply issung 'setenv hwconfig esdhc', and not able to interact with
U-Boot anylonger).
So, but default we assume that the board is a prototype, which is a most
safe assumption. There is no way to determine board revision from a
register, so we use hwconfig.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Originally written by Jason Jin and Mingkai Hu for mpc8536.
When QorIQ based board is configured as a PCIe agent, then unlock/enable
inbound PCI configuration cycles and init a 4K inbound memory window;
so that a PCIe host can access the PCIe agents SDRAM at address 0x0
* Supported in fsl_pci_init_port() after adding pcie_ep as a param
* Revamped copyright in drivers/pci/fsl_pci_init.c
* Mods in 85xx based board specific pci init after this change
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The data being modified was in NOR flash which caused the crash.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
On Chip BootROM support for P1 and P2 series RDB platforms.
This patch is derived from latest On Chip BootROM support on MPC8536DS
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
NAND Boot support for P1 and P2 series RDB platforms.
This patch is derived from NAND Boot support on MPC8536DS.
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Commit 054197ba and later fixes used an array to initialize some of
the MDDRC parameters; however, the use of an array turned out to be a
bad idea as it was not possible to correlate structure entries to
array indices in readable and reliable way. Now we use a struct
instead, which makes this self-explanatory.
Signed-off-by: Wolfgang Denk <wd@denx.de>
The following changes allow U-Boot to fully relocate from flash to
RAM:
- Remove linker scripts' .fixup sections from the .text section
- Add -mrelocatable to PLATFORM_RELFLAGS for all boards
- Define CONFIG_RELOC_FIXUP_WORKS for all boards
Previously, U-Boot would partially relocate, but statically initialized
pointers needed to be manually relocated.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
The MPC8536E is capable of booting from the on-chip ROM - boot from
eSDHC and boot from eSPI. When power on, the porcessor excutes the
ROM code to initialize the eSPI/eSDHC controller, and loads the mian
U-Boot image from the memory device that interfaced to the controller,
such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or
L2SRAM, then boot from it.
The memory device should contain a specific data structure with control
word and config word at the fixed address. The config word direct the
process how to config the memory device, and the control word direct
the processor where to find the image on the memory device, or where
copy the main image to. The user can use any method to store the data
structure to the memory device, only if store it on the assigned address.
The on-chip ROM code will map the whole 4GB address space by setting
entry0 in the TLB1, so the main image need to switch to Address space 1
to disable this mapping and map the address space again.
This patch implements loading the mian U-Boot image into L2SRAM, so
the image can configure the system memory by using SPD EEPROM.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
MPC8536E can support booting from NAND flash which uses the
image u-boot-nand.bin. This image contains two parts: a 4K
NAND loader and a main U-Boot image. The former is appended
to the latter to produce u-boot-nand.bin. The 4K NAND loader
includes the corresponding nand_spl directory, along with the
code twisted by CONFIG_NAND_SPL. The main U-Boot image just
like a general U-Boot image except the parts that included by
CONFIG_SYS_RAMBOOT.
When power on, eLBC will automatically load from bank 0 the
4K NAND loader into the FCM buffer RAM where CPU can execute
the boot code directly. In the first stage, the NAND loader
copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
then loads the main image from NAND flash to RAM or L2SRAM
and boot from it.
This patch implements the NAND loader to load the main image
into L2SRAM, so the main image can configure the RAM by using
SPD EEPROM. In the first stage, the NAND loader copies itself
to the second to last 4K address space, and uses the last 4K
address space as the initial RAM for stack.
Obviously, the size of L2SRAM shouldn't be less than the size
of the image used. If so, the workaround is to generate another
image that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
With this patch we can change QE USB mode without need to hand-edit
the device tree.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This patch fixes various ethernet issues with gigabit links handling
in U-Boot. The workarounds originally implemented by Kim Phillips for
Linux kernel.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Since commit 5c2ff323a9 ("mpc8360emds:
rework LBC SDRAM setup"), LBC SDRAM is available for use in Linux.
Though, it appears that QE Ethernet in Gigabit mode can't transmit
large packets when it tries to work with a data in LBC SDRAM (memtest
didn't discover any issues, is LBC SDRAM just too slow?).
With this patch we can still use the board without DDR memory, but
if DDR is available, we don't use LBC SDRAM.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Martha M Stan <mmarx@silicontkx.com>
Minor cleanup:
Re-ordered default_mddrc_config[] to have matching indices.
This allows to use the same index "N" for source and target fields;
before, we had code like this
out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]);
which always looked like a copy & paste error because 2 != 3.
Also, use NULL when meaning a null pointer.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Using the common 86xx fdt fixups removes some board-specific code and
should make the mpc8610hpcd easier to maintain in the long run.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010
where max DDR data width supported is 64bit.
As a next step the DDR data width initialization would be made more dynamic
with more flexibility from the board perspective and user choice.
Going forward we would also remove the hardcodings for platforms with onboard
memories and try to use the FSL SPD code for DDR initialization.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
On 85xx platforms we shouldn't be using any LAWAR_* defines
but using the LAW_* ones provided by fsl-law.h. Rename any such
uses and limit the LAWAR_ to the 83xx platform as the only user so
we will get compile errors in the future.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
General code cleanup to use in/out IO accessors as well as making
the code that prints out info sane between board and generic fsl pci
code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
So that we can set the NAND loader's relocate stack pointer
to the value other than the relocate address + 0x10000.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Some board ports place TEXT_BASE at a location that would cause the
RESET_VECTOR_ADDRESS not to be at 0xfffffffc when we link. By default
we assume RESET_VECTOR_ADDRESS will be 0xfffffffc if the board doesn't
explicitly set it.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
Refactor the code into a simple bitmask lookup table that determines if
a given PCI controller is enabled and if its in host/root-complex or
agent/end-point mode.
Each processor in the PQ3/MPC86xx family specified different encodings
for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The ddr_pd_cntl isn't defined in any reference manual and thus we wil
remove especially since we set it to 0, which would most likely be its
POR value.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The warning is bogus, so silence it by initializing the 'ret' variable.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The "mac id" command took a 4-character parameter as the identifier string.
However, for any given board, only one kind of identifier is acceptable, so it
makes no sense to ask the user to type it in. Instead, if the user enters
"mac id", the identifier (and also the version, if it's NXID) will
automatically be set to the correct value.
Improve the message that is displayed when EEPROM is read during boot. It now
displays "EEPROM:" and then either an error message or the EEPROM identifier
if successful.
If the identifier in EEPROM is valid, then always reject a bad CRC, even if the
CRC field has not been initialized.
Don't force the MAC address count to MAX_NUM_PORTS or less. Forcing the value
to be changed resulting in an in-memory copy that does not match what's in
hardware, even though the user did not request that change.
Finally, always update the CRC value in the in-memory copy after any field
is changed, so that the CRC is always correct.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Call fsl_pci_init_port() to initialize all the PCIe ports on the board.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
There are really no differences between all the 85xx linker scripts so
we can just move to a single common one. Board code is still able to
override the common one if need be.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The code base adds P1 & P2 RDB platforms support.
The folder and file names can cater to future SOCs of P1/P2 family.
P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series.
Tested following on P2020RDB:
1. eTSECs
2. DDR, NAND, NOR, I2C.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
For historic reasons we had defined some additional PLATFORM_CPPFLAGS like:
PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1
However these are all captured in the config.h and thus redudant. Also
moved common 86xx flags into cpu/mpc86xx/config.mk.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
For historic reasons we had defined some additional PLATFORM_CPPFLAGS
like:
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
However these are all captured in the config.h and thus redudant.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows
before it calls fsl_pci_init. There isn't any reason to just call it
from fsl_pci_init and simplify things a bit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Every platform that calls fsl_pci_init calls pci_setup_indirect before
it calls fsl_pci_init. There isn't any reason to just call it from
fsl_pci_init and simplify things a bit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
All in-tree boards that use this controller have CONFIG_NET_MULTI added
Also:
- changed CONFIG_DRIVER_CS8900 to CONFIG_CS8900
- changed CS8900_BASE to CONFIG_CS8900_BASE
- changed CS8900_BUS?? to CONFIG_CS8900_BUS??
- cleaned up line lengths
- modified VCMA9 command function that accesses the device
- removed MAC address initialization from lib_arm/board.c
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Tested-by: Wolfgang Denk <wd@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
All in-tree boards that use this controller have CONFIG_NET_MULTI added
Also:
- changed CONFIG_DRIVER_SMC911X* to CONFIG_SMC911X*
- cleaned up line lengths
- modified all boards that override weak function in this driver
- added
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Tested-by: Mike Frysinger <vapier@gentoo.org>
Rename sdram_mode_1 to sdram_mode and sdram_cfg_1 to sdram_cfg to match
the 86xx user's manual and other Freescale architectures
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The p2020DS, MPC8536DS, MPC8572DS, MPC8544DS boards are capable of
swizzling the upper address bits of the NOR flash we boot out of which
creates the concept of "virtual" banks. This is useful in that we can
flash a test of image of u-boot and reset to one of the virtual banks
while still maintaining a working image in "bank 0".
The PIXIS FPGA exposes registers on LBC which we can use to determine
which "bank" we are booting out of (as well as setting which bank to
boot out of).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The MPC8641HPCN board is capable of swizzling the upper address bit of
the NOR flash we boot out of which creates the concept of "virtual"
banks. This is useful in that we can flash a test of image of u-boot
and reset to one of the virtual banks while still maintaining a
working image in "bank 0".
The PIXIS FPGA exposes registers on LBC which we can use to determine
which "bank" we are booting out of (as well as setting which bank to
boot out of).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
So far the console API uses the following naming convention:
======Extract======
typedef struct device_t;
int device_register (device_t * dev);
int devices_init (void);
int device_deregister(char *devname);
struct list_head* device_get_list(void);
device_t* device_get_by_name(char* name);
device_t* device_clone(device_t *dev);
=======
which is too generic and confusing.
Instead of using device_XX and device_t we change this
into stdio_XX and stdio_dev
This will also allow to add later a generic device mechanism in order
to have support for multiple devices and driver instances.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Edited commit message.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Since we have simple hwconfig interface now, we don't need
pci_external_arbiter variable any longer.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
This patch simply converts the board to the hwconfig infrastructure.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
fdt_fixup_esdhc() will either disable or enable eSDHC nodes, and
also will fixup clock-frequency property.
Plus, since DR USB and eSDHC are mutually exclusive, we should
only configure the eSDHC if asked through hwconfig.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
This patch adds support for eSDHC on MPC837XERDB boards. The WP
switch doesn't seem to work on RDB boards though, the WP pin is
always asserted (can see the pin state when it's in GPIO mode).
FSL DR USB and FSL eSDHC are mutually exclusive because of pins
multiplexing, so user should specify 'esdhc' or 'dr_usb' options
in the hwconfig environment variable to choose between the
devices.
p.s.
Now we're very close to a monitor len limit (196 bytes left using
gcc-4.2.0), so also increase the monitor len by one sector (64 KB).
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Update serial boot DRAM's Internal RAM, vector table and DRAM in
start.S, serial flash's read status command over SPI and NOR
flash.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Now that we have 3 boards for the MPC512x it turns out that they all
use the very same fixed_sdram() code.
This patch factors out this common code into cpu/mpc512x/fixed_sdram.c
and adds a new header file, include/asm-ppc/mpc512x.h, with some
macros, inline functions and prototype definitions specific to MPC512x
systems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Add support for Freescale's i.MX31 PDK board (a.k.a. 3 stack board).
This patch assumes that some other program performs the actual
NAND boot.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
Acked-by: Fabio Estevam <fabioestevam@yahoo.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
sys_eeprom.c: In function 'do_mac':
sys_eeprom.c:323: warning: dereferencing type-punned pointer will break strict-aliasing rules
sys_eeprom.c: In function 'mac_read_from_eeprom':
sys_eeprom.c:395: warning: dereferencing type-punned pointer will break strict-aliasing rules
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Update 83xx architecture's CONFIG_ECC_INIT_VIA_DDRC references to
CONFIG_ECC_INIT_VIA_DDRCONTROLLER, which other Freescale architectures
use
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
All drivers need to be converted to CONFIG_NET_MULTI.
This patch converts the dm9000 driver.
Signed-off-by: Thomas Smits <ts.smits@gmail.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
We support up to 8 mac addresses in system eeprom, so we define the macro
MAX_NUM_PORTS to limit the mac_count to 8, and update the number of ethxaddr
according to mac_count.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch supports UCC working at RMII mode on PIB board, fixup fdt blob to
support rmii in kernel. It also changes the name of enable_mpc8569mds_qe_mdio to
enalbe_mpc8569mds_qe_uec which is more accurate.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The patch adds support for P2020DS reference platform.
DDR3 interface uses hard-coded initialization rather than SPD
for now and was tested at 667Mhz. Some PIXIS register
definitions and associated code sections need to be fixed.
TSEC1/2/3, NOR flash, MAC/SYS ID EEPROM, PCIE1/2/3 are all
tested under u-boot.
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch adds NAND support to the MPC5121ADS board. Please
note that the image size increased since NAND support didn't
fit in the current image size (256k).
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Use the standard lowercase "xx" capitalization that other Freescale
architectures use for CPU defines to prevent confusion and errors
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit changes the MPC512x code to use I/O accessor calls (i.e.
out_*() and in_*()) instead of using deprecated pointer accesses.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: John Rigby <jcrigby@gmail.com>
We rename the board so we use a consistent name in U-Boot and in
Linux. Also, we use this opportunity to move the board into the
Freecale vendor directory.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: John Rigby <jcrigby@gmail.com>
Many of the help messages were not really helpful; for example, many
commands that take no arguments would not print a correct synopsis
line, but "No additional help available." which is not exactly wrong,
but not helpful either.
Commit ``Make "usage" messages more helpful.'' changed this
partially. But it also became clear that lots of "Usage" and "Help"
messages (fields "usage" and "help" in struct cmd_tbl_s respective)
were actually redundant.
This patch cleans this up - for example:
Before:
=> help dtt
dtt - Digital Thermometer and Thermostat
Usage:
dtt - Read temperature from digital thermometer and thermostat.
After:
=> help dtt
dtt - Read temperature from Digital Thermometer and Thermostat
Usage:
dtt
Signed-off-by: Wolfgang Denk <wd@denx.de>
all arm boards except a few use the same cpu linker script
so move it to cpu/$(CPU)
that could be overwrite in following order
SOC
BOARD
via the corresponding config.mk
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
MPC8569 UART1 signals are muxed with PortF bit[9-12], we need to define
those pins before using UART1.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The BCSR17[7] = 1 will unlock the write protect of FLASH.
The WP# pin only controls the write protect of top/bottom sector,
That is why we can save env, but we can't write the first sector
before the patch.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Currently the clk_adj is 6 (3/4 cycle), The settings will cause
the DDR controller hang at the data init. Change the clk_adj
from 6 to 4 (1/2 cycle), make the memory system stable.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Rename the pci header for FSL HW so we can move some prototypes
in there and stop doing explicit externs
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Use CONFIG_MP instead of CONFIG_NUM_CPUS to match 85xx
* Introduce determine_mp_bootpg() helper. We'll need this to address a
bug introduced in v2009.03 with 86xx MP booting. We have to make sure
to reserve the region of memory used for the MP bootpg() so other
u-boot code doesn't use it.
* Added dummy versions of cpu_reset(), cpu_status() & cpu_release() to
allow cmd_mp.c to build and work. In the future we should look at
implementing all these functions. This could be common w/85xx if we
use spin tables on 86xx.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We're missing the board_lmb_reserve definitions that allow
cpu_mp_lmb_reserve to be called; this means that Linux
is free to reallocate reserved pages. Linux currently boots
because we're getting lucky - the page we've reserved is
high enough in memory that it isn't allocated by Linux
while we still need it to be in existence.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch adds MPC8569MDS board support. The UART, QE UEC1 and UEC2, BRD
EEPROM on I2C2 bus, PCI express and DDR3 SPD are supported in this patch.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Hillel Avni <Hillel.Avni@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The NAND flash on the TQM8548_BE modules requires a short delay after
running the UPM pattern like the MPC8360ERDK board does. The TQM8548_BE
requires a further short delay after writing out a buffer. Normally the
R/B pin should be checked, but it's not connected on the TQM8548_BE.
The corresponding Linux FSL UPM driver uses similar delay points at the
same locations. To manage these extra delays in a more general way, I
introduced the "wait_flags" field allowing the board-specific driver to
specify various types of extra delay.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
This patch adds support for multi-chip NAND devices to the FSL-UPM
driver. The "dev_ready" callback of the "struct fsl_upm_nand" is now
called with the argument "chip_nr" to allow testing the proper chip
select line. The NAND support of the MPC8360ERDK is updated as well.
No other boards are currently using the FSL UPM driver.
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
A recent gcc added a new unaligned rodata section called '.rodata.str1.1',
which needs to be added the the linker script. Instead of just adding this
one section, we use a wildcard ".rodata*" to get all rodata linker section
gcc has now and might add in the future.
However, '*(.rodata*)' by itself will result in sub-optimal section
ordering. The sections will be sorted by object file, which causes extra
padding between the unaligned rodata.str.1.1 of one object file and the
aligned rodata of the next object file. This is easy to fix by using the
SORT_BY_ALIGNMENT command.
This patch has not be tested one most of the boards modified. Some boards
have a linker script that looks something like this:
*(.text)
. = ALIGN(16);
*(.rodata)
*(.rodata.str1.4)
*(.eh_frame)
I change this to:
*(.text)
. = ALIGN(16);
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
This means the start of rodata will no longer be 16 bytes aligned.
However, the boundary between text and rodata/eh_frame is still aligned to
16 bytes, which is what I think the real purpose of the ALIGN call is.
Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
The Nand flash was unable to read and write properly
due to Nand Chip Select (nCE) setup was in reverse
order. Also, increase the Nand time out value to 60.
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
These were left in accidentally, and are not really useful unless the
code is as broken as it was when it was being developed.
Signed-off-by: Andy Fleming <afleming@freescale.com>
The SerDes initialization should be finished before negating the reset
signal according to the reference manual. This isn't an issue on real
hardware, but we'd better stick to the specifications anyway.
Suggested-by: Liu Dave <DaveLiu@freescale.com>
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
On MPC8377E-RDB and MPC8378E-RDB boards we have PCIe and mini-PCIe
slots. Let's support them.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
