4 Commits

Author	SHA1	Message	Date
Simon Glass	74e53e0e9b	rockchip: Add a simple 'clock' command ... Add a command that displays the PLLs and their current rate. Signed-off-by: Simon Glass <sjg@chromium.org>	2016-01-21 20:42:36 -07:00
Simon Glass	ad443b7290	rockchip: Don't skip low-level init ... At present the low-level init is skipped on rockchip. Among other things this means that the instruction cache is left disabled. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>	2016-01-21 20:42:36 -07:00
huang lin	be1d5e0388	rockchip: rk3036: Add core Soc start-up code ... rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288	2015-12-01 08:07:22 -07:00
Simon Glass	2444dae587	rockchip: Add core SoC start-up code ... Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass <sjg@chromium.org>	2015-09-02 21:28:24 -06:00