This patch removes the x86 architecture specific GD flags
(GD_FLG_COLD_BOOT & GD_FLG_WARM_BOOT), as they are not used. Only
GD_FLG_COLD_BOOT is referenced in coreboot.c but assigned in start16.S.
But the coreboot target does not use start16.S at all and boots directly
from the 32-bit start code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This file contains lots of internal details about the environment. Most
code can include env.h instead, calling the functions there as needed.
Rename this file and add a comment at the top to indicate its internal
nature.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
[trini: Fixup apalis-tk1.c]
Signed-off-by: Tom Rini <trini@konsulko.com>
This declaration is only used in three files. Although it relates to
malloc() it is actually only used during malloc() init. It uses CONFIG
options including CONFIG_ENV_ADDR which are defined only in environment.h
so this header must be included anyway, for TOTAL_MALLOC_LEN to be
correct.
Nove it to environment.h to simplify the common file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
The setting up MTRRs have already been done in previous
Slim Bootloader stages.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Add a new device tree which has very minimum nodes
- x86 reset
- x86 tsc_timer
- x86 pci
- Slim Bootloader serial
Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Slim Bootloader already calibrated TSC and provides it to U-Boot.
Therefore, U-Boot does not have to re-calibrate TSC.
Configuring tsc_base and clock_rate makes x86 tsc_timer driver bypass
TSC calibration and use the provided TSC frequency.
- Get TSC frequency from performance info hob
- Set tsc_base and clock_rate for tsc_timer driver
Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Slim Bootloader provides serial port info thru its HOB list pointer.
All these HOBs are eligible for Slim Bootloader based board only.
- Get serial port information from the serial port info HOB
- Leverage ns16550 driver with slimbootloader specific platform data
Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Slim Bootloader provides memory map info thru its HOB list pointer.
Configure memory size and relocation memory from the HOB data, and
provide e820 entries as well.
- Get memory size from the memory map info HOB
- Set available top memory lower than 4GB for U-Boot relocation
- Provide e820 entries from the memory map info HOB
Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
FSP (CONFIG_HAVE_FSP) and Slim Bootloader (CONFIG_SYS_SLIMBOOTLOADER)
consume HOB (CONFIG_USE_HOB) data from the each HOB list pointer.
Add a common HOB library in lib/hob.c and include/asm/hob.h.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Use existing EFI_GUID and efi_guid_t instead of struct efi_guid.
This is pre-work before making a common HOB library.
- Change 'struct efi_guid' to efi_guit_t
- Remove 'struct efi_guid'
- Define GUIDs with EFI_GUID() macro
- Use guidcmp() instead of compare_guid()
- Remove compare_guid()
Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested on MinnowMax
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This slimbootloader CPU type is to enable U-Boot as a payload which
runs on top of Slim Bootloader (https://github.com/slimbootloader).
The Slim Bootloader is designed with multi-stage architecture for
the execution from reset vector to OS booting, and supports QEMU,
Apollolake, Whiskeylake and Coffeelake platforms consuming Intel
FSP (https://github.com/IntelFsp) for silicon initialization
including CAR and memory initialization.
The Slim Bootloader generates new HOB (Hand Off Block) which are
serial port info, memory map info, performance data info and so on,
and passes it to a Payload. U-Boot as a payload will use these HOB
information for basic initialization such as serial console.
As an initial commit,
- Add CONFIG_SYS_SLIMBOOTLOADER to enable slimbootloader CPU type
- Add new arch/x86/cpu/slimbootloader directory with minimum codes
- Get hob_list pointer from Slim Bootloader
Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Intel Tangier has a shared DMA controller that, according to Microsoft spec,
has to be presented in CSRT table.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
ACPI has a capability to specify DMA parameters for DMA channel consumers.
To enable this for Intel Edison, describe GP DMA device in ACPI table
in order to get an ACPI handle to it in OS.
This works in conjunction with CSRT, which must be in align with DSDT.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Here is a stub function that generates an empty CSRT. If the target platform
provides acpi_fill_csrt() function, it will be used to populate the table.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Enable SD slot on Intel Edison platform.
By default firmware doesn't put device on active state. Thus,
we have to do this explicitly.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This struct is not defined in this header file. Add a forward declaration
so that it can be included in any context.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This breaks Intel Edison to work. It gets laggish and unable to boot kernel.
Reverts commit 665cb18ea6 for now
till better solution will be proposed.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
coreboot makes it possible to add own entries into coreboot's
table at a per mainboard basis. As there might be some custom
ones it makes sense to provide a way to process them.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Add nvdata drivers for the TPM and RTC as used on samus. These are needed
for Chromium OS verified boot on samus.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add the required CPU code so that TPL builds correctly. Also update the
SPL code to deal with being booted from TPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When TPL finishes it needs to jump to SPL with the stack set up correctly.
Add a function to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The early init should only happen once. Update the probe method to
deal with TPL, SPL and U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With the use of a phandle we can outdent the device tree nodes a little.
Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The standard image generated by U-Boot on x86 is u-boot.rom. Add a
separate image called image.bin for verified boot. This supports
verification in TPL of which SPL/U-Boot to start, then jumping to the
correct one, with SPL setting up the SDRAM and U-Boot proper providing
the user interface if needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add TPL binaries to the device x86 binman desciption. When enabled, TPL
will start first, doing the 16-bit init, then jump to SPL and finally
U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This report is normally generated by U-Boot proper. Correct the condition
here so that it respects the Kconfig options for bootstage.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The MTRRs are normally set up in U-Boot proper, so avoid setting them up
in SPL as well.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Update the Makefie rules to ensure that the correct files are built when
TPL is being used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When the MRC cache fails to save it is useful to have some debugging info
to indicate what when wrong. Add some more debug() calls.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When SPL is used to set up the memory controller we want to save the MRC
data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a
function to handle that.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds
and identifies the CPU.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Allow broadwell to build for SPL and include the reference code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present broadwell only supports booting straight into U-Boot proper.
Add a separate init file to boot from SPL into U-Boot proper, and select
it when SPL is in use.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present we support having 16-bit init be in SPL or U-Boot proper, but
not TPL. Add support for this so that TPL can boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When a previous phase of U-Boot has run we need to adjust the init of
subsequent states to avoid messing up the CPU state.
Add a new version of the start logic for SPL, when it boots from TPL
(start_from tpl.c) and a new version for U-Boot when it boots from SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Split the CPU init into two parts - the 'full' init which happens in the
first U-Boot phase, and the rest of the init that happens on subsequent
stages.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present the debug UART is set up in sdram.c which is not the best place
since it has nothing in particular to do with SDRAM. Since we want to
support initing this in SPL too, move it to a common file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: added 'broadwell' tag in the commit title]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
At present, for broadwell, SDRAM is always set up in U-Boot proper since
the 64-bit mode (which uses SDRAM init in SPL) is not supported.
Update the code to allow SDRAM init in SPL instead so that U-Boot proper
can be loaded into SDRAM and run from there. This allows U-Boot to be
compressed to reduce space, since it is not necessary to run it directly
from flash. It could later allow us to support 64-bit U-Boot on broadwell.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add debugging during SDRAM init so that problems are easier to
diagnose.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add an arch-specific handoff header so that we can use the HANDOFF feature
on x86 devices.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some boards want to use TPL as the first phase of U-Boot. This allows
selection of A or B SPL phases, thus allowing the memory init to be
upgraded in the field.
Add a new Kconfig option for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present only chromebook_link64 supports SPL. It is useful to eb able to
support both TPL and SPL to implement verified boot on x86.
Enable the options for both along with some suitable default options
needed to boot through these phases.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add labels for these nodes so that board DT files can reference them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
