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2 Commits

Author SHA1 Message Date
Marek Vasut
a8535c306c arm: socfpga: Fix delay in freeze controller 
Based on observation, this udelay(20) was apparently too high and caused
subsequent failure to calibrate DDR when U-Boot was compiled with certain
toolchains. Lowering this delay fixed the problem.

Instead of permanently lowering the delay, calculate the correct delay
based on the original comment, that is, obtain EOSC1 frequency and use
it to calculate the precise delay.

Signed-off-by: Marek Vasut <marex@denx.de>
 2015-08-23 11:56:19 +02:00
Masahiro Yamada
05a217212b ARM: socfpga: move SoC sources to mach-socfpga 
Our recent trend is to collect SoC files into arch/arm/mach-(SOC).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
 2015-05-07 05:21:12 +02:00