2 Commits

Author	SHA1	Message	Date
Michal Simek	dcd8a102ca	xilinx: Sync symbols location in defconfigs ... CONFIG_DEBUG_UART_BASE and CONFIG_DEBUG_UART_CLOCK have changed that's why this sync. Signed-off-by: Michal Simek <michal.simek@xilinx.com>	2018-06-04 11:25:30 -04:00
Ezequiel Garcia	c66f5620e6	arm: zynq: Add support for Bitmain Antminer S9 control board ... This is control board on Bitmain Antminer S9. There are 3 board variables with 256MB, 512MB and 1024MB DDR. DDR memory is automatically detected with using get_with using get_ram_size(). Bitmain is using 16MB space for FPGA which is handled via reserved-memory. Also U-Boot is allocating 16B for storing bootcounts. Watchdog is started but never service in U-Boot. SPL MMC is working. SPL NAND is not working because it is not supported as of now. Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>	2018-05-31 13:50:39 +02:00