4 Commits

Author	SHA1	Message	Date
Jian Li	3f63d27c17	imx8mp: Disables use of MR4 TUF flag (MR4[7]) bit ... In uMCTL2 Databook, for LPDDR4, it is recommended to set this register to 1. This can avoid ddr bandwidth is lower after booting with running for a while. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jian Li <jian.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>	2020-07-14 15:23:46 +08:00
Jian Li	5865d14dde	imx8mp: DDR performance tunning ... 1. set SCHED.rdwr_idle_gap=0 2. set SCHED.pageclose=1 Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Jian Li <jian.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>	2020-07-14 15:23:46 +08:00
Jian Li	dd2f41370d	imx8mp: enable rd_port_urgent ... Need to enable read urgent for NoC panic signal Signed-off-by: Jian Li <jian.li@nxp.com Signed-off-by: Peng Fan <peng.fan@nxp.com>	2020-07-14 15:23:46 +08:00
Peng Fan	439321b264	imx: add i.MX8MP EVK board ... Add basic i.MX8MP EVK board support U-Boot SPL 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800) power_pca9450b_init DDRINFO: start DRAM init DDRINFO:ddrphy calibration done DDRINFO: ddrmix config done Normal Boot Failed to find clock node. Check device tree WDT: Not found! Trying to boot from BOOTROM image offset 0x8000, pagesize 0x200, ivt offset 0x0 U-Boot 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800) CPU: Freescale i.MX8MP rev1.0 at 1000 MHz Reset cause: POR Model: NXP i.MX8MPlus EVK board DRAM: 6 GiB MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial Out: serial Err: serial Net: No ethernet found. Hit any key to stop autoboot: 0 u-boot=> mmc list FSL_SDHC: 1 (SD) FSL_SDHC: 2 Signed-off-by: Peng Fan <peng.fan@nxp.com>	2020-01-08 13:20:09 +01:00