This patch adds support for dynamic configuration of PCIe ports for the
AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe
boards Yucca & Katmai and the 405EX board Kilauea.
This dynamic configuration is done via the "pcie_mode" environement
variable. This variable can be set to "EP" or "RP" for endpoint or
rootpoint mode. Multiple values can be joined via the ":" delimiter.
Here an example:
pcie_mode=RP:EP:EP
This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2
as endpoint.
Per default Yucca will be configured as:
pcie_mode=RP:EP:EP
Per default Katmai will be configured as:
pcie_mode=RP:RP:REP
Per default Kilauea will be configured as:
pcie_mode=RP:RP
Signed-off-by: Tirumala R Marri <tmarri@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch enables the fdt support on the AMCC Kilauea eval board.
Additionally now EBC ranges fdt fixup is included to support NOR
FLASH mapping via the Linux physmap_of driver.
This Kilauea port now support booting arch/ppc and arch/powerpc
Linux kernels. The default environment "net_nfs" is for arch/ppc
and "net_nfs_fdt" is for arch/powerpc. In the long run, arch/ppc
support will be removed.
Signed-off-by: Stefan Roese <sr@denx.de>
These files were introduced with the IBM 405GP but are currently used on all
4xx PPC platforms. So the name doesn't match the content anymore. This patch
renames the files to 4xx_pci.c/h.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.
(2) This patch renames the functions from 440spe_ to 4xx_ with a
little additional cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.
(1) This patch renames the files from 440spe_pcie to 4xx_pcie
Signed-off-by: Stefan Roese <sr@denx.de>
Some commands for the STK52xx base board try to access the SM501 grafic
controller. But the TQM5200S has no grafic controller (only the TQM5200
and the TQM5200B have). This patch deactivates the commands accessing
the SM501 for the TQM5200S.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Some commands for the STK52xx base board try to access the SM501 grafic
controller. But the TQM5200S has no grafic controller (only the TQM5200
and the TQM5200B have). This patch deactivates the commands accessing
the SM501 for the TQM5200S.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
The pxa255_idp being an old unmaintained board showed several issues:
1. CONFIG_INIT_CRITICAL was still defined.
2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined.
3. Symbol flash_addr was undeclared.
4. The boards lowlevel_init function was still called memsetup.
5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000.
6. Using -march=armv5 instead of -march=armv5te resulted in lots of
'target CPU does not support interworking' warnings on recent compilers.
7. The PXA's serial driver redefined FFUART, BTUART and STUART used as
indexes rather than the register definitions from the pxa-regs header
file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to
avoid any ambiguities.
8. There were several redefinition warnings concerning ICMR, OSMR3,
OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file.
9. The board configuration file was rather outdated.
10. The part header file defined the vendor, product and revision arrays
as unsigned chars instead of just chars in the block_dev_desc_t
structure.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
Per AN3221 (MPC5200B SDRAM Initialization and Configuration), the SDelay
register must be written a value of 0x00000004 as the first step of the
SDRAM contorller configuration.
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
Ensure that __got_start points to top of the `.got', and __got_end points
to bottom as well, so that we never fail to count num_got_entries.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
On the MPC85xx CDS we have two issues:
1. The device tree fixup code did not check to see if the property we are
trying to update is actually found. Its possible that it would update
random memory starting at 0.
2. Newer Linux kernel's have moved the location of the PCI nodes to be
sibilings of the soc node and not children. The explicit PATH to the PCI
node would not be found for these device trees. Add the ability to handle
both paths. In the future we shouldn't handle such fixups by explicit path.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The I2C bootstrap values that can be setup via the "bootstrap" command,
were setup incorrect regarding the generation of the internal sync PCI
clock. The values for PLB clock == 133MHz were slighly incorrect and the
values for PLB clock == 166MHz were totally incorrect. This could
lead to a hangup upon booting while PCI configuration scan.
This patch fixes this issue and configures valid PCI divisor values
for the sync PCI clock, with respect to the provided external async
PCI frequency.
Here the values of the formula in the chapter 14.2 "PCI clocking"
from the 440EPx users manual:
AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz
33MHz async PCI frequency:
PLB = 133:
=> 32 <= 44.3 <= 65 (div = 3)
PLB = 166:
=> 32 <= 55.3 <= 65 (div = 3)
66MHz async PCI frequency:
PLB = 133:
=> 65 <= 66.5 <= 132 (div = 2)
PLB = 166:
=> 65 <= 83 <= 132 (div = 2)
Signed-off-by: Stefan Roese <sr@denx.de>
The BCSR status bit for the 66MHz PCI operation was correctly
addressed (MSB/LSB problem). Now the correct currently setup
PCI frequency is displayed upon bootup.
This patch also fixes this problem on Rainier & Yellowstone, since these
boards use the same souce code as Sequoia & Yosemite do.
Signed-off-by: Stefan Roese <sr@denx.de>
The ATSTK1000-specific flash driver intializes bi_flashstart,
bi_flashsize and bi_flashoffset, but other flash drivers, like the CFI
driver, don't.
Initialize these in board_init_r instead so that things will still be
set up correctly when we switch to the CFI driver.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
With recent toolchains, the environment sectors were no longer aligned to
sector boundaries. The reason was a combination of two bugs:
1) common/environment.c assumed that CONFIG_TQM8xxL would be defined
for all TQM8xxL and TQM8xxM boards. But "include/common.h", where
this gets defined, is not included here (and cannot be included
without causing lots of problems).
Added a new #define CFG_USE_PPCENV for all boards which really
want to put the environment is a ".ppcenv" section.
2) The linker scripts just include environment.o, silently assuming
that the objects in that file are really in the order in which
they are coded in the C file, i. e. "environment" first, then
"redundand_environment", and "env_size" last. However, current
toolchains (GCC-4.x) reorder the objects, causing the environment
data not to start on a flash sector boundary:
Instead of: we got:
40008000 T environment 40008000 T env_size
4000c000 T redundand_environment 40008004 T redundand_environment
40010000 T env_size 4000c004 T environment
Note: this patch fixes just the first part, and cures the alignment
problem by making sure that "env_size" gets placed correctly. However,
we still have a potential issue because primary and redundant
environment sectors are actually swapped, i. e. we have now:
40008000 T redundand_environment
4000c000 T environment
40010000 T env_size
This shall be fixed in the next version.
Signed-off-by: Wolfgang Denk <wd@denx.de>
- 'pciconfighost' is set by default in order to be able to scan bridges
behind the primary host/PCIe
- 'pciscandelay' env variable is recognized to allow for user-controlled
delay before the PCIe bus enumeration; some peripheral devices require a
significant delay before they can be scanned (e.g. LSI8408E); without the
delay they are not detected
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
- correct configuration space mapping
- correct bus numbering
- better access to config space
Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the
first device on the first bus. We now allow to configure up to 16 buses;
also, scanning for devices behind the PCIe-PCIe bridge is supported, so
peripheral devices farther in hierarchy can be identified.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Affects boards: icecube (lite5200), jupiter, motionpro, tqm5200
Tested on: lite5200b
Note: the fixup functions have not been moved to a common place. This
patch is targeted for immediate merging as in solves a build issue, but
the final name/location of the fixups is still subject to debate. I
propose to merge this now, and move the fixups in the next merge window
to be usable by all targets.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
The RTC on the M1575 ULI chipset requires a dummy read before
we are able to talk to the RTC. We accomplish this by adding a
second memory region to the PHB the ULI is on and read from it.
The second region is added to maintain compatiabilty with Linux's
view of the PCI memory map.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is
set to non-zero, because it doesn't support MRM (memory-read-
multiple) correctly. We now added the possibility to configure
this register in the board config file, so that the default value
of 8 can be overridden.
Here the details of this patch:
o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow
board-specific settings. As an example the sequoia board requires 0.
Idea from Stefan Roese <sr@denx.de>.
o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the
PCI IO-space. Obtained from Stefan Roese <sr@denx.de>.
o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set
CFG_PCI_CACHE_LINE_SIZE to 0.
Signed-off-by: Gary Jennejohn <garyj@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Restore CONFIG_EXTRA_ENV_SETTINGS definition which contains the
correct consoledev needed for linux boot.
Standardize on fdt{file,addr} var to hold dtb file name.
Set PCI inbound memory region from CFG_MEMORY_{BUS,PHYS}.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
if a board/$(VENDOR)/common/Makefile exists, build it.
also add the first such case, board/freescale/common/Makefile, to
handle building board-shared EEPROM, PIXIS, and MDS-PIB code, as
dictated by board configuration.
thusly get rid of alternate build dir errors such as:
FATAL: can't create /work/wd/tmp/u-boot-ppc/board/freescale/mpc8360emds/../common/pq-mds-pib.o: No such file or directory
by putting the common/ mkdir command in its proper place (the common
Makefile). Common bits from existing individual board Makefiles have
been removed.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
omap2420h4 switched to cfi, so remove old (already disabled) flash.c
and flash_probe() calls in env_flash.c.
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
define there own I/O functions.
(Needed for the pcs440ep board).
- The default I/O Functions are again 8 Bit accesses.
- Added CONFIG_CMD_IDE for the pcs440ep Board.
Signed-off-by: Heiko Schocher <hs@denx.de>
This patch adds support for the 2nd EEPROM (AT24C128) on the lwmon5
board. Now the "eeprom" command can be used to read/write from/to this
device. Additionally a new command was added "eepromwp" to en-/disable
the write-protect of this 2nd EEPROM.
The 1st EEPROM is not affected by this write-protect command.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds support for the matrix keyboard on the lwmon5 board.
Since the implementation in the dsPCI is kind of compatible with the
"old" lwmon board, most of the code is copied from the lwmon
board directory.
Signed-off-by: Stefan Roese <sr@denx.de>
platforms wishing to display RAM diagnostics in addition to size,
can do so, on one line, in their own board_add_ram_info()
implementation.
this consequently eliminates CONFIG_ADD_RAM_INFO.
Thanks to Stefan for the hint.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
add board_add_ram_info, to make memory diagnostic output more
consistent. u-boot banner output now looks like:
DRAM: 256 MB (DDR1, 64-bit, ECC on)
and for boards with SDRAM on the local bus, a line such as this is
added:
SDRAM: 64 MB (local bus)
also replaced some magic numbers with their equivalent define names.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The patch split the PIB init code from pci.c to a single file board/freescale/common/pq-mds-pib.c
And add Qoc3 ATM card support for MPC8360EMDS and MPC832XEMDS board.
Signed-off-by Tony Li <tony.li@freescale.com>
The PCIe bus that the ULI M1575 is connected to has no possible way of
needing more than the fixed amount of IO & Memory space needed by the ULI.
So make it use far less IO & memory space and have it use the shared LAW. This
free's up a LAW for PCIe1 IO space. Also reduce the amount of IO space needed
by each bus.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
It looks like we had a merge issue that duplicated a bit of code
in ft_board_setup. Also, we need to set CONFIG_HAS_ETH0 to get
the MAC address properly set in the device tree on boot for TSEC1
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Minor cleanups to confirm to the u-boot coding style.
Some german expressions -> english.
HCU5 enforces a unique IP adress for a given slot in the rack.
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
Make ecc initialisation robust, as DDR2-ECC errors may be generated
while zeroing the RAM.
Return 16 bytes (a cacheline) less than the available memory, as the
board and/or PPC440EPx might have problems accessing the last bytes.
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
