4 Commits

Author	SHA1	Message	Date
Alex Marginean	430a5542f3	armv8: ls1028a_serdes: Add few missing serdes protocols ... Add serdes protocol 0x7777, 0x9999, 0xb998, 0xbb56 to supported list. These protocols are supported and functional but they trigger a warning in U-Boot console at boot because they are not on this list. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>	2020-01-24 14:28:26 +05:30
Hou Zhiqiang	116f75c7b3	armv8: ls1028a: Updated serdes configuration for 0x13BB ... In SerDes protocol 0x13BB, lane C was erroneously assigned to PCIE1, this is now updated to PCIE2 Fixes: 36f50b7523 ("armv8: ls1028a: Add other serdes protocal support") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>	2019-09-12 16:15:42 +05:30
Xiaowei Bao	36f50b7523	armv8: ls1028a: Add other serdes protocal support ... Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>	2019-06-19 12:54:56 +05:30
Yuantian Tang	d4ad111dc4	armv8: ls1028a: Add NXP LS1028A SoC support ... Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>	2019-05-22 12:24:24 +05:30