The AT91RM9200-EK Evaluation Board supports the AT91RM9200
ARM9-based 32-bit RISC microcontroller and enables real-time code development
and evaluation.
Here is the chip page on Atmel website:
http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507
with
- NOR (cfi driver)
- DataFlash
- USB OHCI
- Net
- I2C (hard)
Signed-off-by: Ulf Samuelsson <ulf@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
When testing a u-boot binary that hasn't been booted from the bootrom, we
have to make sure the bootstruct structure has sane storage space. If we
don't, the initcode will crash when it tries to dereference an invalid
pointer.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Match determine_mp_bootpg() that was added for 86xx. We need this to
address a bug introduced in v2009.03 with 86xx MP booting. We have to
make sure to reserve the region of memory used for the MP bootpg() so
other u-boot code doesn't use it.
Also added a comment about how cpu_reset() is dealing w/an errata on
early 85xx MP HW.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Use CONFIG_MP instead of CONFIG_NUM_CPUS to match 85xx
* Introduce determine_mp_bootpg() helper. We'll need this to address a
bug introduced in v2009.03 with 86xx MP booting. We have to make sure
to reserve the region of memory used for the MP bootpg() so other
u-boot code doesn't use it.
* Added dummy versions of cpu_reset(), cpu_status() & cpu_release() to
allow cmd_mp.c to build and work. In the future we should look at
implementing all these functions. This could be common w/85xx if we
use spin tables on 86xx.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of
LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage,
then invalidate it after LBCR bit 13 is set.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
- support mirrored DIMMs, not support register DIMMs
- test passed on P2020DS board with MT9JSF12872AY-1G1D1
- test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
1. wr_lat
UM said the total write latency for DDR2 is equal to
WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1.
so, the WR_LAT = CL - 1;
2. rd_to_pre
we missed to add the ADD_LAT for DDR2 case.
Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Divisor field is called PTV not PVT.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Current u-boot top of tree builds with warnings/errors for
the following boards:
ads5121 cpci5200 mecp5200 v38b IAD210 MBX MBX860T NX823
RPXClassic debris PN62
following patch solves this.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
On boards which have the environment in eeprom, i2c_init() is called
before the console and RAM are initialized.
Suppress printfs until the console is initialized.
Signed-off-by: Jon Smirl <jonsmirl@gmail.com>
Acked-by: Heiko Schocher <hs@denx.de>
When initializing the core clocks, stick external memory into self-refresh.
This gains us a few cool things:
- support suspend-to-RAM with Linux
- reprogram clocks automatically when doing "go" on u-boot.bin in RAM
- make sure settings are stable before flashing new version
- finally fully unify initialize startup code path between LDR/non-LDR
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some newer Blackfins (like the BF51x) do not have an on-chip voltage
regulator, so do not attempt to program the memory as if it does.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
If the board config does not specify an explicit EBIU_SDBCTL value, set it
up with sane values based on other configuration options.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Workaround anomaly 432:
The bfrom_SysControl() firmware function does not clear the SIC_IWR1
register before executing the PLL programming sequence. Therefore, any
interrupt enabled in the SIC_IWR1 register prior to the call to
bfrom_SysControl() can prematurely terminate the idle sequence required
for the PLL to relock properly. SIC_IWR0 is properly handled.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The Boot ROM uses EVT1 as the entry point so set that rather than having
to use a tiny jump block in the default EVT1 location.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The jtag tstc operation was checking the hardware to see if data is
available from it (which is fine for the jtag getc operation), but the
higher layers need to know whether any data is available. Since we have
to read up to 4 bytes at a time from the hardware, the higher layers need
to know they can consume the cached bytes as well.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
AT91sam9g20 is an evolution of the at91sam9260 with a faster clock speed.
The AT91SAM9G20-EK board is an updated revision of the AT91SAM9260-EK board.
It is essentially the same, with a few minor differences.
Here is the chip page on Atmel website:
http://www.atmel.com/dyn/products/product_card.asp?part_id=4337
Signed-off-by: Justin Waters <justin.waters@timesys.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
