The RK3399 boot code (running as AArch64) poses a bit of a challenge
for SPL image generation:
* The BootROM will start execution right after the 4-byte header (at
the odd instruction word loaded into SRAM at 0xff8c2004, with the
'RK33' boot magic residing at 0xff8c2000).
* The default padding (during ELF generation) for AArch64 is 0x0,
which is an illegal instruction and the .text section needs to be
naturally aligned (someone might locate a 64bit constant relative
to the section start and unaligned loads trigger a fault for all
privileged modes of an ARMv8)... so we can't simply define the
CONFIG_SPL_TEXT_BASE option to the odd address (0xff8c2004).
* Finally, we don't want to change the values used for padding of
the SPL .text section for all ARMv8 targets to the instruction
word encoding 'nop', as this would affect all padding in this
section and might hide errors that would otherwise quickly trigger
an illegal insn exception.
To deal with this situation, we modify the rkimage generation to
- understand the fact that the RK3399 needs to pad the header to an
8 byte boundary using an AArch64 'nop'
- the necessary logic to adjust the header_size (which controls the
location where the payload is copied into the image) and to insert
this padding (AArch64 insn words are always little-endian) into
the image following the 4-byte header magic.
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
The RC4 encoding works on full blocks, but the calculation of the
starting offset and size are needlessly complicated by using a
reference value known to be offset into a block by the size of the
header and then correcting for the (hard-coded) size of the header
(i.e. 4 bytes).
We change this over to use the RK_SPL_HDR_START directly (which is
known to be on a block boundary).
X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Rockchip SoCs allow the spl code to be rc4-encoded, not only the
image header, but only newer SoCs allow this encoding to be disabled.
The rk3188 is not part of those and requires its boot code to be
rc4-encoded with the regular key. So add the ability to do this
encoding via a setting on a per-soc basis when building spl images.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Our chips may have different spl size and spl header, so
use imagename(passed by "mkimage -n") to select them now.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
The Rockchip boot ROM could load & run an initial spl loader,
and continue to load a second level boot-loader(which stored
right after the initial loader) when it returns.
Modify idblock generation code to support it.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Our chips may have different max spl size and spl header, so
we need to add configs for that.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h,
Added $(if...) to tools/Makefile to fix widespread build breakage
Signed-off-by: Simon Glass <sjg@chromium.org>
Series-changes: 8
- Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h,
- Add $(if...) to tools/Makefile to fix widespread build breakage
The Rockchip boot ROM requires a particular file format for booting from SPI.
It consists of a 512-byte header encoded with RC4, some padding and then up
to 32KB of executable code in 2KB blocks, separated by 2KB empty blocks.
Add support to mkimage so that an SPL image (u-boot-spl-dtb.bin) can be
converted to this format. This allows booting from SPI flash on supported
machines.
Signed-off-by: Simon Glass <sjg@chromium.org>
