Commit Graph

13912 Commits

Author SHA1 Message Date
Vikas Manocha
adcc90b401 stm32f746-disco: enable flash support
This patch enables embedded flash for stm32f746 discovery board.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2016-03-26 18:49:28 -04:00
Vikas Manocha
9ecb0c416c stm32: stm32f4: move flash driver to mtd driver location
Same flash driver can be used by other stm32 families like stm32f7.
Better place for this driver would be mtd driver location.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
2016-03-26 18:49:28 -04:00
Sam Protsenko
f9d0fd8a56 usb: gadget: Move CONFIG_USB_GADGET to Kconfig
The description was borrowed from kernel. "tristate" type was changed
to "bool" (I believe we don't support modules for u-boot yet, right?).
CONFIG_USB_GADGET requires CONFIG_USB to be defined too, so add it along
as well.

Definitions were added to defconfig files in a way that
"make savedefconfig" generates exactly the same file as used defconfig.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
[trini: Add zynq_zc702 conversion]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-25 15:29:48 -04:00
Tom Rini
a6164205ee Merge git://www.denx.de/git/u-boot-marvell 2016-03-25 12:57:18 -04:00
Stefan Roese
aea02abec5 arm: mvebu: theadorable: Add StratixV FPGA programming support
This patch adds support for Altera StratixV bitstream programming. 2 FPGAs
are connected to the SPI busses. This patch uses board specific write
code to program the bitstream via SPI direct write mode.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-03-24 09:48:34 +01:00
Stefan Roese
ff9c4c535a fpga: altera: Add StratixV support
This patch adds support for programming of the StratixV FPGAs. Programming
is done in this case (board theadorable) via SPI. The board may provide
board specific code for bitstream programming.

This StratixV support will be used by the theadorable board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-03-24 09:47:43 +01:00
Peter Korsgaard
371b9e9c39 ARM: sheevaplug: correct nand partition layout
Commit 1e3d640316 (ARM: sheevaplug: redefine MTDPARTS) changed the partition
layout (without any description why), but didn't change the offset/size to
load the kernel from or the root=/dev/mtdblockX in the bootargs.

The 3MB forseen for a kernel is furthermore too little. A 4.4 build of
mvebu_v5_defconfig is 3.6MB:

-rw-r--r-- 1 peko peko 3.6M Jan 16 20:24 uImage.kirkwood-sheevaplug

When device tree support for sheevaplug was added to the kernel in commit
ee514b381e (ARM: Kirkwood: Add dts files for Sheevaplug and eSATA
Sheevaplug) a default flash partition layout (used if mtdparts= isn't passed
on the command line / CONFIG_MTD_CMDLINE_PARTS isn't enabled) with 1MB for
u-boot / environment, 4MB for the kernel and the rest for the rootfs, so use
that layout here and adjust the kernel loading to match.

Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-03-24 09:26:10 +01:00
Tom Rini
b5b84be8a7 Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2016-03-23 18:35:11 -04:00
Hans de Goede
1eae8f66ff sunxi: Enable realtek phy support
Enable building of drivers/net/phy/realtek.c so that realtek phys
get properly initialized.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Hans de Goede
4bb656e9dd include/dt-bindings: Sync some files with the kernel
This commit syncs the dt-bindings/input/* headers with the kernel (v4.5)
and adds dt-bindings/clock/sun4i-a10-pll2.h, both are necessary for newer
sunxi dts files to build.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-03-23 22:04:13 +01:00
Masahiro Yamada
d085ecd61b ARM: uniphier: switch to raw U-Boot image
Now everything is done to load a raw U-Boot proper image instead of
an mkimage-processed one (as far as I tested on NAND, eMMC, NOR).

The SPL already knows the load address of the U-Boot proper without
parsing its uImage header because the load address is defined by
CONFIG_SYS_TEXT_BASE, assuming that the two images are generated from
the same build.

My main motivation of this switch is to use u-boot-with-spl.bin, a
concatenation of u-boot-spl.bin and u-boot.bin.  (I wish there were
a concatenation of u-boot-spl.bin and u-boot.img...)  Anyway, this
commit would be useful for one-shot image burn.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:41 +09:00
Masahiro Yamada
cbbc2d80fc ARM: uniphier: add NOR boot support
This allows to boot from NOR flash (or SRAM) with help of an external
loader (NOR-loader).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:45:41 +09:00
Masahiro Yamada
ea65c98050 ARM: uniphier: drop PH1- prefix from CONFIG options and file names
The current CONFIG names like "CONFIG_ARCH_UNIPHIER_PH1_PRO4" is too
long.  It would not hurt to drop "PH1_" because "UNIPHIER_" already
well specifies the SoC family.  Also, rename files for consistency.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:42:13 +09:00
Masahiro Yamada
013dcc7863 ARM: uniphier: fix bogus comment
This comment line is telling the opposite of the logic.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:37:02 +09:00
Masahiro Yamada
69856c53aa ARM: uniphier: remove commented out define
This TODO is no longer useful.  CONFIG_SYS_NS16550_SERIAL is just
ignored on DM serial.

If one wants to use the 16550A UART device on the UniPhier Micro
Support Card, it can be enabled by CONFIG_SYS_NS16550 via Kconfig.
Please notice CONFIG_SPL_OF_TRANSLATE must be enabled as well and
the device tree must be treaked in order to use the NS16550 serial
on SPL.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-24 01:37:01 +09:00
Bin Meng
0764f24ae6 net: Move CONFIG_RTL8169 to Kconfig
Introduce CONFIG_RTL8169 in Kconfig and move over boards' defconfig
to use that.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Stephen Warren <swaren@nvidia.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-03-22 12:19:53 -04:00
Bin Meng
86e9dc86b1 net: Move CONFIG_RTL8139 to Kconfig
Introduce CONFIG_RTL8139 in Kconfig and move over boards' defconfig
to use that.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
[trini: Fixup MPC8641HPCN* and r2dplus configs]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-22 12:19:27 -04:00
Vagrant Cascadian
a6f70a3d14 Fix spelling of "transferred".
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-22 12:16:16 -04:00
Tom Rini
8a7367acca cmd: Fix license command
The license command isn't usually built and has a few problems:
- The rules to generate license.h haven't worked in a long time,
  re-write these based on the bmp_logo.h rules.
- 'tok' is unused and the license text size has increased
- bin2header.c wasn't grabbing unistd.h to know the prototype for
  read().

Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-03-22 12:16:13 -04:00
Eric Anholt
cd0fa5bff8 serial: pl01x: Add support for devices with the rate pre-configured.
For Raspberry Pi, we had the input clock rate to the pl011 fixed in
the rpi.c file, but it may be changed by firmware due to user changes
to config.txt.  Since the firmware always sets up the uart (default
115200 output unless the user changes it), we can just skip our own
uart init to simplify the boot process and more reliably get serial
output.

Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
2016-03-22 12:16:12 -04:00
Simon Glass
9a6598daaf Drop various features when the command line is not available
Some features are only useful or meaningful when the command line is
present. Ensure that these features are not compiled in when CONFIG_CMDLINE
is not enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-22 12:16:11 -04:00
Simon Glass
fb24112c19 Allow command code to compile to nothing
When CONFIG_CMDLINE is disabled we need to remove all the command-line
code. Most can be removed by dropping the appropriate linker lists from the
images, but sub-commands must be dealt with specially.

A simple mechanism is used to avoid 'unused static function' errors.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-22 12:16:10 -04:00
Vitaly Andrianov
b8dafa2209 ti: k2g: increase phy autoneg timeout
After power cycle of a K2G EVM dhcp fails due to a auto-negotiation
timeout. This commit increases the timeout to fix the issue.

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-03-22 12:16:07 -04:00
Tom Rini
55926ddd18 Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2016-03-22 12:14:27 -04:00
Wenbin Song
ceded371c8 armv8/ls1043aqds: Enable ID_EEPROM support for ls1043aqds
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:15 -07:00
Alison Wang
f8008f144b arm: ls102xa: Enable CONFIG_SYS_CONSOLE_IS_IN_ENV support
CONFIG_SYS_CONSOLE_IS_IN_ENV needs to be enabled, so we could set stdout
environment variable to specify the vga for the console output when
LCD/HDMI is connected to the boards.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:14 -07:00
Shengzhou Liu
eb118807a4 driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete
Add support of address parity for DDR4 UDIMM or discrete memory.
It requires to configurate corresponding MR5[2:0] and
TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig,
e.g. hwconfig=fsl_ddr:parity=on.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:13 -07:00
Stuart Yoder
eeb5b1ad82 pci: make pci_get_hose_head() available to external users
Put pci_get_hose_head() prototype in header so it is available to
external users, allowing them to find and iterate over all pci
controllers.

Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:12 -07:00
York Sun
ed77b7045e boards: ls2080: Fix default bootargs
A white space is missing in multiple-line string for bootargs.

Signed-off-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:12 -07:00
Shaohui Xie
abc7d0f75c armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY
To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:10 -07:00
Reinhard Pfau
a119357c43 strider: use optimised bus timing for FPGA access
Use optimised bus timing for FPGA access.

Signed-off-by: Reinhard Pfau <reinhard.pfau@gdsys.cc>

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2016-03-21 09:20:37 +01:00
Dirk Eibach
4709805657 strider: Define pca593x widths
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2016-03-21 09:20:31 +01:00
Tom Rini
83d95b67d3 Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2016-03-20 18:09:34 -04:00
Stefan Roese
93d9fc26cb arm: socfpga: sr1500: Misc updates (SPI speed, env location)
This patch makes the following changes to the SR1500 board port:

- Update defconfig to support SPI NOR (use make savedefconfig).
- Increase SPI speed to a maximum of 100MHz for faster system
  bootup.
- Change environment location, so that its not between SPL and
  main U-Boot. This way the combined SPL / U-Boot image can
  be used for updates.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
2016-03-20 18:01:11 +01:00
Stefan Roese
ead2fb29e8 arm: socfpga: Allow boards to define a custom environment size
This patch makes it possible that boards can define a board-specific env
size. This is used by the SR1500 SoCFPGA board port.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Marek Vasut <marex@denx.de>
2016-03-20 18:01:10 +01:00
Marek Vasut
b72041ccf8 arm: socfpga: Fix SR1500 env position
Move the inclusion of the common socfpga configuration file further
down in the sr1500 configuration, so that the socfpga_common.h can
check if environment is in SPI NOR and it's location is defined and
if it is not, define default location.

This fixes "arm: socfpga: Enabling U-Boot environment support in QSPI"
which introduced a minor warning.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
2016-03-20 18:01:10 +01:00
Chin Liang See
ec8b75281b arm: socfpga: Enabling U-Boot environment support in QSPI
Enabling the support of storing U-Boot environment
within serial NOR flash. By default, its still
store into SDMMC

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
2016-03-20 18:01:10 +01:00
Stefan Roese
c998da0d67 usb: Change power-on / scanning timeout handling
This patch changes the USB port scanning procedure and timeout
handling in the following ways:

a)
The power-on delay in usb_hub_power_on() is now reduced to a value of
max(100ms, "hub->desc.bPwrOn2PwrGood * 2"). The code does not wait
using mdelay, instead usb_hub_power_on() will wait before querying
the device in the scanning loop later. The total timeout for this
hub, which is 1 second + "hub->desc.bPwrOn2PwrGood * 2" is calculated
and will be used in the following per-port scanning loop as the timeout
to detect active USB devices on this hub.

b)
Don't delay the minimum delay (for power to stabilize) in
usb_hub_power_on(). Instead skip querying these devices in the scannig
loop until the delay time is reached.

c)
The ports are now scanned in a quasi parallel way. The current code did
wait for each (unconnected) port to reach its timeout and only then
continue with the next port. This patch now changes this to scan all
ports of all USB hubs quasi simultaneously. For this, all ports are added
to a scanning list. This list is scanned until all ports are ready
by either a) reaching the connection timeout (calculated earlier), or
by b) detecting a USB device. This results in a faster USB scan time as
the recursive scanning of USB hubs connected to the hub that's currently
being scanned will start earlier.

One small functional change to the original code is, that ports with
overcurrent detection will now get rescanned multiple times
(PORT_OVERCURRENT_MAX_SCAN_COUNT).

Without this patch:
starting USB...
USB0:   USB EHCI 1.00
scanning bus 0 for devices... 9 USB Device(s) found

time: 20.163 seconds

With this patch:
starting USB...
USB0:   USB EHCI 1.00
scanning bus 0 for devices... 9 USB Device(s) found

time: 1.822 seconds

So ~18.3 seconds of USB scanning time reduction.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
2016-03-20 18:00:45 +01:00
Michal Simek
59b35ddd26 dm: ns16550: Add support for reg-offset property
reg-offset is the part of standard 8250 binding in the kernel.
It is shifting start of address space by reg-offset.
On Xilinx platform this offset is typically 0x1000.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Moved the new field to the end of the struct to avoid problems:
Signed-off-by: Simon Glass <sjg@chromium.org>
2016-03-17 21:27:39 -06:00
Stefan Roese
82ceba2ca2 x86: Add congatec conga-QA3/E3845-4G (Bay Trail) support
This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM,
installed on the congatec Qseven 2.0 evaluation carrier board
(conga-QEVAL).

Its port is very similar to the MinnowboardMAX port and also uses
the Intel FSP as described in doc/README.x86.

Currently supported are the following interfaces / devices:
- UART (via Winbond legacy SuperIO chip on carrier board)
- Ethernet (PCIe Intel I210 / E1000)
- SPI including SPI NOR as boot-device
- USB 2.0
- SATA via U-Boot SCSI IF
- eMMC
- Video (HDMI output @ 800x600)
- PCIe

Not supported yet is:
- I2C
- USB 3.0

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
374e78efb0 x86: Add support for the samus chromebook
This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.

Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard

Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).

The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
69ca6fd850 x86: dts: Drop memory SPD compatible string
This is not needed now that the memory controller driver has the SPD data
in its own node.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
93a1c3cd54 x86: Fix a header nit in x86-chromebook.h
There is an extra line in the comment in the header. Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
a69ed4e6a1 x86: Use white on black for the console on chromebooks
This is a little easier on the eyes, particularly when the backlight is set
to maximum.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
2e4fc2b2cc x86: Add a default address for reference code
Add an address which can be used for loading and running the reference code
when needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
b24f5c4f27 x86: broadwell: Add a pinctrl driver
GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.

The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
779653b0cb x86: Drop all the old pin configuration code
We don't need this anymore - we can use device tree and the new pinconfig
driver instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
8226a3e99f input: i8042: Make sure the keyboard is enabled
Add one more step into the init sequence. This fixes the keyboard on samus,
which otherwise does not work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
4974a6ff04 pci: Correct a few comments and nits
Two comments are missing a parameter and there is an extra blank line. Also
two of the region access macros are misnamed. Correct these problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Simon Glass
319dba1f4d pci: Add functions to update PCI configuration registers
It is common to read a config register value, clear and set some bits, then
write back the updated value. Add functions to do this in one step, for
convenience.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00