3 Commits

Author	SHA1	Message	Date
Matthew McClintock	abbe536ebc	powerpc/p1010rdb: nandboot: compare SVR properly ... We were not comparing the SVRs properly previously. This comparison will properly shift the SVR and mask off the E bit This fixes the boot output to show the correct DDR bus width: 512 MiB (DDR3, 16-bit, CL=5, ECC off) instead of 512 MiB (DDR3, 32-bit, CL=5, ECC off) Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>	2012-08-23 10:24:17 -05:00
Matthew McClintock	9c6b47d53e	p1014rdb: set ddr bus width properly depending on SVR ... Currently, for NAND boot for the P1010/4RDB we hard code the DDR configuration. We can still dynamically set the DDR bus width in the nand spl so the P1010/4RDB boards can boot from the same u-boot image Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>	2012-08-23 10:24:16 -05:00
Dipen Dudhat	d793e5a840	powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB ... And various defines to enable NAND support and NAND spl code for the P1010RDB platform. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	2011-09-29 19:01:04 -05:00