3 Commits

Author	SHA1	Message	Date
Andy Fleming	ab5cda9f88	Remove LBC_CACHE_BASE from 8544 DS ... The 8544 DS doesn't have any cacheable Local Bus memories set up. By mapping space for some anyway, we were allowing speculative loads into unmapped space, which would cause an exception (annoying, even if ultimately harmless). Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the problem. Signed-off-by: Andy Fleming <afleming@freescale.com>	2008-07-14 11:21:33 -05:00
Kumar Gala	859a86a25c	85xx/86xx: Move to dynamic mgmt of LAWs ... With the new LAW interface (set_next_law) we can move to letting the system allocate which LAWs are used for what purpose. This makes life a bit easier going forward with the new DDR code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>	2008-06-11 01:52:23 -05:00
Kumar Gala	4bcae9c92a	85xx: convert MPC8544 DS over to use new LAW init code ... Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	2008-01-16 23:21:55 -06:00