This was causing problems for some people.
Signed-off-by: Alain Gravel <agravel@fulcrummicro.com>
Signed-off-by: Dan Wilson <dwilson@fulcrummicro.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
On the MPC85xx CDS we have two issues:
1. The device tree fixup code did not check to see if the property we are
trying to update is actually found. Its possible that it would update
random memory starting at 0.
2. Newer Linux kernel's have moved the location of the PCI nodes to be
sibilings of the soc node and not children. The explicit PATH to the PCI
node would not be found for these device trees. Add the ability to handle
both paths. In the future we shouldn't handle such fixups by explicit path.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
On the MPC8568 MDS we use ttyS0, UART0, etc. as the standard configured
console. Make it so we match that config what we tell Linux as the early
STDOUT console.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The mpc85xx start code uses some magic numbers that we actually
have #defines for in <config.h> so use those instead.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add MPC8360EMDS_ATM_config and MPC832XEMDS_ATM_config into
Makfile and MAKEALL
Signed-off-by: Tony Li <tony.li@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
As a direct correlation exists between DDR DIMM slots
and SPD EEPROM addresses used to configure them, use
the individually defined SPD_EEPROM_ADDRESS* values to
determine if a DDR DIMM slot should have its SPD
configuration read or not.
Effectively, this now allows for 1 or 2 DIMM slots
per memory controller.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Some USB keys need to be switched off before loading the kernel
otherwise they can remain in an undefined status which prevents them
to be correctly recognized by the kernel.
Signed-off-by: Rodolfo Giometti <giometti@linux.it>
The I2C bootstrap values that can be setup via the "bootstrap" command,
were setup incorrect regarding the generation of the internal sync PCI
clock. The values for PLB clock == 133MHz were slighly incorrect and the
values for PLB clock == 166MHz were totally incorrect. This could
lead to a hangup upon booting while PCI configuration scan.
This patch fixes this issue and configures valid PCI divisor values
for the sync PCI clock, with respect to the provided external async
PCI frequency.
Here the values of the formula in the chapter 14.2 "PCI clocking"
from the 440EPx users manual:
AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz
33MHz async PCI frequency:
PLB = 133:
=> 32 <= 44.3 <= 65 (div = 3)
PLB = 166:
=> 32 <= 55.3 <= 65 (div = 3)
66MHz async PCI frequency:
PLB = 133:
=> 65 <= 66.5 <= 132 (div = 2)
PLB = 166:
=> 65 <= 83 <= 132 (div = 2)
Signed-off-by: Stefan Roese <sr@denx.de>
The BCSR status bit for the 66MHz PCI operation was correctly
addressed (MSB/LSB problem). Now the correct currently setup
PCI frequency is displayed upon bootup.
This patch also fixes this problem on Rainier & Yellowstone, since these
boards use the same souce code as Sequoia & Yosemite do.
Signed-off-by: Stefan Roese <sr@denx.de>
At 133 MHz the current SDRAM refresh rate is too fast
(measured 4 * 1.17 us).
CFG_MAMR_PTA changes from 39 to 97. This result
in a refresh rate of 4 * 7.8 us at the default clock
50 MHz. At 133 MHz the value will be then 4 * 2.9 us.
This is a compromise until a new method is found to
adjust the refresh rate.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
The ATSTK1000-specific flash driver intializes bi_flashstart,
bi_flashsize and bi_flashoffset, but other flash drivers, like the CFI
driver, don't.
Initialize these in board_init_r instead so that things will still be
set up correctly when we switch to the CFI driver.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
CFG_MEMTEST_START uses weird magic involving gd, which fails to
compile. Use hardcoded values instead (we actually know how much RAM
we have on board.)
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
