Commit ac337168a unified functions to flush and invalidate dcache by
range. These two functions were no-ops for SoCs other than 4xx and
MPC86xx. Adding these functions seemed to be correct but introduced
issues in some drivers when the dcache was flushed. While the root
cause was under investigation, these functions were disabled in
Commit cb1629f91a for affected SoCs, including the MPC85xx, to make
the various drivers work.
On the T208x USB stopped working after v2016.07 was pulled. After
re-enabling the dcache functions for the MPC85xx it started working
again. The USB and DPPA Ethernet drivers have been seen as
operational after this change but other drivers cannot be tested.
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz>
Cc: Marek Vasut <marex@denx.de>
Cc: York Sun <york.sun@nxp.com>
Reviewed-by: York Sun <york.sun>
The read-only-write-enable bit is set by default and must be cleared
to prevent overwriting read-only registers. This should be done
immediately after resetting the PCI Express controller.
Reviewed-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz>
[York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig]
Reviewed-by: York Sun <york.sun@nxp.com>
Core hang occurs when using L1 stashes. Workaround is to disable L1
stashes so software uses L2 cache for stashes instead.
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Darwin Dingel <darwin.dingel@alliedtelesis.co.nz>
Cc: York Sun <york.sun@nxp.com>
[York S: Move SYS_FSL_ERRATUM_A007907 to Kconfig]
Reviewed-by: York Sun <york.sun@nxp.com>
This option should not really be user selectable. Note that on PowerPC
we currently only need BOARD_LATE_INIT when CHAIN_OF_TRUST is enabled so be
conditional on that.
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> (for UniPhier)
Introduce board/freescale/common/Kconfig so that we have a single place
for CONFIG options that are shared between ARM and PowerPC NXP platforms.
Cc: York Sun <york.sun@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Move all of the status LED feature to drivers/led/Kconfig.
The LED status definitions were moved from the board configuration
files to the defconfig files.
TBD: Move all of the definitions in the include/status_led.h to the
relevant board's defconfig files.
Tested boards: CL-SOM-AM57x, CM-T335
Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.
Signed-off-by: York Sun <york.sun@nxp.com>
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing
usage in ls102xa and fsl-layerscape. Remove all powerpc macros in
config header and board header files.
Signed-off-by: York Sun <york.sun@nxp.com>
Add option SYS_FSL_ERRATUM_ESDHC111, SYS_FSL_ERRATUM_ESDHC13,
SYS_FSL_ERRATUM_ESDHC135, SYS_FSL_ERRATUM_ESDHC_A001 to mmc Kconfig.
Move existing macros to related Kconfig.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate bk4r1]
Signed-off-by: Tom Rini <trini@konsulko.com>
Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s]
Signed-off-by: Tom Rini <trini@konsulko.com>
Instead of define CONFIG_SYS_FSL_SEC_COMPAT in header files for PowerPC
and ARM SoCs, move it to Kconfig under the driver.
Signed-off-by: York Sun <york.sun@nxp.com>
Use Kconfig SYS_PPC_E500_DEBUG_TLB and clean up existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate 8572]
Signed-off-by: Tom Rini <trini@konsulko.com>
When setting the compatible property for the L2 cache ensure that we
follow the documented binding by setting both
"<chip>-l2-cache-controller" and "cache" as values.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Enable ERRATUM_A009942 workaround for B-series and T-series platforms.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
- add additional function erratum_a009942_check_cpo to check if the
board needs tuning CPO calibration for optimal setting.
- move ERRATUM_A009942(with revision to check cpo_sample option) from
fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts.
- move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c
- remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
[YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500]
Reviewed-by: York Sun <york.sun@nxp.com>
Commit e2f88dfd2d ("libfdt: Introduce new ARCH_FIXUP_FDT option")
allows us to skip memory setup of DTB, but a problem for ARM is that
spin_table_update_dt() and psci_update_dt() are skipped as well if
CONFIG_ARCH_FIXUP_FDT is disabled.
This commit allows us to skip only fdt_fixup_memory_banks() instead
of the whole of arch_fixup_fdt(). It will be useful when we want to
use a memory node from a kernel DTB as is, but need some fixups for
Spin-Table/PSCI.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed build error for x86:
Signed-off-by: Simon Glass <sjg@chromium.org>
Some header files have this macro defined conditionally and
redefined unconditionally. Remove all existing definitions.
Signed-off-by: York Sun <york.sun@nxp.com>
This configuration has been moved into Kconfig for mpc85xx, and
dropped for mpc86xx. Remove the default value in config.h.
Signed-off-by: York Sun <york.sun@nxp.com>
