4 Commits

Author	SHA1	Message	Date
huang lin	be1d5e0388	rockchip: rk3036: Add core Soc start-up code ... rk3036 only 4K size SRAM for SPL, so only support timer, uart, sdram driver in SPL stage, when finish initial sdram, back to bootrom.And in rk3036 sdmmc and debug uart use same iomux, so if you want to boot from sdmmc, you must disable debug uart. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed build error for chromebook_jerry, firefly-rk3288: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Fix build error for chromebook_jerry, firefly-rk3288	2015-12-01 08:07:22 -07:00
huang lin	53c45f0ca2	rockchip: add rk3036 sdram driver ... add rk3036 sdram driver so we can set up sdram in SPL Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>	2015-12-01 08:07:22 -07:00
huang lin	0b374c8dc8	rockchip: rk3036: Add a simple syscon driver ... Add a driver that provides access to system controllers Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>	2015-12-01 08:07:22 -07:00
huang lin	2bc00e016e	rockchip: rk3036: Add Soc reset driver ... We can reset the Soc using some CRU (clock/reset unit) register. Add support for this. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>	2015-12-01 08:07:22 -07:00