We change default settings for egiga on mgcoge3un.
The reason we need this is that we have the gig port on mgcoge3un
connected using a back-to-back pair of PHYs. There are no magnetics and
because of that the port has to be run with a fixd configuration and
auto-negotiation must be disabled. In the default mode the egiga driver
uses autoneg to determine port speed - which defaults to 1G (we need
100M full duplex).
Add wait for the GPIO line connected to mgcoge3ne before
starting mgcoge3un. A board specific ethernet present function
was added, because on this board ethernet is always present.
The BOCO FPGA access was enhanced and changed to use register
definitions.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Acked-by: Heiko Schocher <hs@denx.de>
cc: Wolfgang Denk <wd@denx.de>
cc: Detlev Zundel <dzu@denx.de>
cc: Prafulla Wadaskar <prafulla@marvell.com>
The mgcoge2un target was only an intermediate step to mgcoge3un.
For this reason the mgcoge2un support was moved to mgcoge3un,
because it isn't needed to support both targets.
We add the BootROM init file for the mgcoge3un memphis RAM.
We also move the suen3 and suen8 boards into the correct category
in the MAINTAINERS file.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Acked-by: Heiko Schocher <hs@denx.de>
cc: Wolfgang Denk <wd@denx.de>
cc: Detlev Zundel <dzu@denx.de>
cc: Prafulla Wadaskar <prafulla@marvell.com>
