Commit Graph

25 Commits

Author SHA1 Message Date
Kim Phillips
88ad3fd91c net: tsec - fix dereferencing type-punned pointer will break strict-aliasing rules warning
fix this gcc 4.4 warning:

tsec.c: In function 'tsec_init':
tsec.c:200: warning: dereferencing type-punned pointer will break strict-aliasing rules

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-07-22 22:53:44 -07:00
Zach LeRoy
091dc9f6ad tsec: Add support for BCM5482S PHY
Signed-off-by: Zach LeRoy <zleroy@xes-inc.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-06-15 00:13:54 -07:00
Paul Gortmaker
0452352df1 tsec: report when there is no vendor specific PHY support
Commit af1c2b84 added a generic phy support, with an ID of zero
and a 32 bit mask; meaning that it will match on any PHY ID.

The problem is that there is a test that checked if a matching
PHY was found, and if not, it printed the non-matching ID.
But since there will always be a match (on the generic PHY,
worst case), this test will never trip.

In the case of a misconfigured PHY address, or of a PHY that
isn't explicitly supported outside of the generic support,
you will never see the ID of 0xffffffff, or the ID of the
real (but unsupported) chip.  It will silently fall through
onto the generic support.

This change makes that test useful again, and ensures that
the selection of generic PHY support doesn't happen without
some sort of notice.  It also makes it explicitly clear that
the generic PHY must be last in the PHY table.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2009-03-09 18:08:04 -05:00
Pieter Henning
736323a490 Added Vitesse VSC8211 definitions to TSEC driver
Added the struct containing PHY settings for the Vitesse VSC8211 phy to
the phy_info list in tsec.c

Signed-off-by: Pieter Henning <phenning@vastech.co.za>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-02-22 23:49:33 -08:00
Andy Fleming
9e5be8214b tsec: Fix a bug in soft-resetting
SOFT_RESET must be asserted for at least 3 TX clocks.  Usually, that's about 30
clock cycles, so it's been mostly working.  But we had no guarantee, and at
slower bitrates, it's just over a microsecond (over 1000 clock cycles).  This
enforces a 2 microsecond gap between assertion and deassertion.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-02-09 22:52:32 -08:00
Ron Madrid
12a8b9db12 Marvell 88E1118 interrupt fix
This patch adjusts the LED control so that interrupt lines are not reading LEDs
and effectively causing indefinite interrupts to the controller.

Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-01-28 23:59:28 -08:00
Anatolij Gustschin
23afaba65e net: tsec: Fix Marvell 88E1121R phy init
This patch tries to ensure that phy interrupt pin
won't be asserted after booting. We experienced
following issues with current 88E1121R phy init:

Marvell 88E1121R phy can be hardware-configured
to share MDC/MDIO and interrupt pins for both ports
P0 and P1 (e.g. as configured on socrates board).
Port 0 interrupt pin will be shared by both ports
in such configuration. After booting Linux and
configuring eth0 interface, port 0 phy interrupts
are enabled. After rebooting without proper eth0
interface shutdown port 0 phy interrupts remain
enabled so any change on port 0 (link status, etc.)
cause assertion of the interrupt. Now booting Linux
and configuring eth1 interface will cause permanent
phy interrupt storm as the registered phy 1 interrupt
handler doesn't acknowledge phy 0 interrupts. This
of course should be fixed in Linux driver too.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-12-04 22:51:54 -08:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Andre Schwarz
c9d6b69253 enable 10/100M at VSC8601 at tsec driver
Currently VSC8601 doesn't link with 10/100M partners if the
EEPROM/Strapping is not set up.
Setting the auto-neg register fixes this.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-10-13 22:29:37 -07:00
Peter Tyser
ce47eb402c Support for multiple SGMII/TBI interfaces for TSEC ethernet
Fix TBI PHY accesses to use the proper offset in CPU register space. The
previous code would incorrectly access the TBI PHY by reading/writing to CPU
register space at the same location as would be used to access external PHYs.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andy Fleming <afleming@freescale.com>
2008-09-16 11:32:45 -05:00
Andy Fleming
2abe361c03 Add SGMII support to the tsec
Adds support for configuring the TBI to talk properly with the SerDes.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-02 21:18:15 -07:00
Andy Fleming
75b9d4ae0d Pass in tsec_info struct through tsec_initialize
The tsec driver contains a hard-coded array of configuration information
for the tsec ethernet controllers.  We create a default function that works
for most tsecs, and allow that to be overridden by board code.  It creates
an array of tsec_info structures, which are then parsed by the corresponding
driver instance to determine configuration.  Also, add regs, miiregs, and
devname fields to the tsec_info structure, so that we don't need the kludgy
"index" parameter.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-02 21:18:15 -07:00
Andy Fleming
dd3d1f56a0 tsec: Move tsec.h to include/
This is to prepare the way for board code passing in the tsec_info structure

Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-02 21:18:15 -07:00
Sergei Poselenov
d23dc394aa PHY: Add support for the M88E1121R Marvell chip.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-09-02 21:18:14 -07:00
Shinya Kuribayashi
3b904ccb93 net: Conditional COBJS inclusion of network drivers
Replace COBJS-y with appropriate driver config names.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-06-09 23:21:05 -07:00
Ron Madrid
290ef64368 Add Marvell 88E1118 support for TSEC
Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-05-23 20:25:19 -07:00
Wolfgang Denk
7c0773fde6 drivers/net/tsec.c: Fix typo.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-05-04 00:35:15 +02:00
Andre Schwarz
9acde129cc TSEC: add config options for VSC8601 RGMII PHY
The Vitesse VSC8601 RGMII PHY has internal delay for both Rx
and Tx clock lines. They are configured using 2 bits in extended
register 0x17.
Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have
been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay.

Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: Andy Fleming <afleming@freescale.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
--

 drivers/net/tsec.c |    6 ++++++
 drivers/net/tsec.h |    3 +++
 2 files changed, 9 insertions(+), 0 deletions(-)
2008-05-03 23:27:04 +02:00
Tor Krill
2d934ea51f Add Vitesse 8601 support to TSEC driver
Add phy_info for Vitesse VSC8601.
Add config option, CFG_VSC8601_SKEWFIX, to enable RGMII skew timing compensation.

Signed-off-by: Tor Krill <tor@excito.com>
Reviewed-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-03-31 23:11:46 -04:00
Anton Vorontsov
c7604783b2 tsec: fix link detection for the RTL8211B PHY
RTL8211B sets link state register after autonegotiation complete,
so with bootdelay=0 RTL8211B will report lack of the link.

To fix this, we should wait for aneg to complete, even if the
link is currently down.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25 19:16:48 -05:00
Dave Liu
18ee320ff6 TSEC: Add the support for RealTek RTL8211B PHY
Add the support of RealTek RTL8211B PHY, the RTL8211B
PHY only supports RGMII and MII mode.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-01-16 17:05:52 -05:00
michael.firth@bt.com
55fe7c57a8 TSEC driver: Change MDIO support to allow access to any PHYs on the MDIO bus
The current TSEC driver limits MDIO access to the devices that have been configured as attached
to a TSEC MAC. This patch allows access to any PHY device on the MDIO bus through the 'mii' commands.

Signed-off-by: Michael Firth <michael.firth@bt.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-01-16 16:51:35 -05:00
Ben Warren
422b1a0160 Fix Ethernet init() return codes
Change return values of init() functions in all Ethernet drivers to conform
to the following:

    >=0: Success
    <0:  Failure

All drivers going forward should return 0 on success.  Current drivers that
return 1 on success were left as-is to minimize changes.

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Acked-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Acked-By: Timur Tabi <timur@freescale.com>
2008-01-10 01:06:02 +01:00
Dave Liu
19580e660c mpc83xx: Add the support of MPC837xEMDS board
The MPC837xEMDS board support:
* DDR2 400MHz hardcoded and SPD init
* Local bus NOR Flash
* I2C, UART, MII and RTC
* eTSEC RGMII
* PCI host

Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-01-08 09:55:39 -06:00
Jean-Christophe PLAGNIOL-VILLARD
2439e4bfa1 drivers/net : move net drivers to drivers/net
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2007-11-25 18:35:17 +01:00