Commit Graph

5 Commits

Author SHA1 Message Date
Masahiro Yamada
a55957b9ad ARM: uniphier: move PLLCTRL register macros to each SoC .c file
The new SoC PXs3 changed the address of PLL, but still uses the
same PLL name.  We can not define SC_*PLLCTRL in the common header.
Move them to per-SoC .c file.  Also, fix some PLL comments.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
546197b986 ARM: uniphier: replace <common.h> with <linux/delay.h> in pll settings
The #include <common.h> was added for mdelay().  Later, the declaration
of mdelay was moved to <linux/delay.h> by commit 5bc516ed66 ("delay:
collect {m, n, u}delay declarations to include/linux/delay.h").

There is no need to include <common.h> now.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-08-30 09:03:11 +09:00
Masahiro Yamada
bc64795804 ARM: uniphier: set up charge pump current for MPLL of LD11 SoC
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-02-23 09:00:16 +09:00
Masahiro Yamada
6c22742d3d ARM: uniphier: enable SSC for DPLL (DRAM PLL) on LD11 SoC
For Electro-Magnetic Compatibility test.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-10 10:03:23 +09:00
Masahiro Yamada
c72f4d4c2e ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious
   SPL memory footprint)
 - Adjust CPLL/MPLL to the final tape-out frequency
 - Set the Cortex-A53 clock to the maximum frequency since it is
   running at 500MHz (SPLL/4) on startup

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-09-23 01:00:23 +09:00