* add's at91_emac (AT91RM9200) network driver (NET_MULTI api)
* enable driver with CONFIG_DRIVER_AT91EMAC
* generic PHY initialization
* modify AT91RM9200 boards to use NET_MULTI driver
* the drivers has been tested with LXT971 Phy and DM9161 Phy at MII and RMII
interface
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
* prepare joining at91 and at91rm9200
* add modified copy of soc files to cpu/arm920t/at91 to make
possible to compile at91rm9200 boards in at91 tree instead
of at91rm9200
* add header files with c structure defs for AT91 MC, ST and TC
* the new cpu files are using at91 c structure soc access
* please read README.soc-at91 for details
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
* add a real AT91 GPIO driver instead of header inline code
* resolve the mixing of port and pins
* change board config files to use new driver
* add macros to gpio to realize backward compatibility
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
The structure was missing a reserved entry (not listed in the manual,
actually), so the last registers had a wrong offset. This prevented
all swlocked registers to be modified as swlock is last in the structure.
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Every omap3 board config file declared the global variable gpmc_cfg.
This changes moves the declaration to a better location in the
arch dependent header file cpu.h.
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* add's at91_emac (AT91RM9200) network driver (NET_MULTI api)
* enable driver with CONFIG_DRIVER_AT91EMAC
* generic PHY initialization
* modify AT91RM9200 boards to use NET_MULTI driver
* the drivers has been tested with LXT971 Phy and DM9161 Phy at
MII and RMII interface
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The EMAC IP on DM365, DM646x and DA830 is slightly different
from that on DM644x. This change updates the DaVinci EMAC driver
so that EMAC becomes operational on SOCs with EMAC v2.
Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
SPEAr310 and SPEAr320 SoCs contain an EMI controller to interface
Paraller NOR flashes. This patch adds the support for this IP
The standard CFI driver is used to interface with NOR flashes
Signed-off-by: Vipin <vipin.kumar@st.com>
This patch adds the support to read and write mac id from i2c
memory.
For reading:
if (env contains ethaddr)
pick env ethaddr
else
pick ethaddr from i2c memory
For writing:
chip_config ethaddr XX:XX:XX:XX:XX:XX writes the mac id
in i2c memory
Signed-off-by: Vipin <vipin.kumar@st.com>
SPEAr600 SoC support contains basic spear600 support along with the
usage of following drivers
- serial driver(UART)
- i2c driver
- smi driver
- nand driver(FSMC)
- usbd driver
Signed-off-by: Vipin <vipin.kumar@st.com>
SPEAr SoCs contain an FSMC controller which can be used to interface
with a range of memories eg. NAND, SRAM, NOR.
Currently, this driver supports interfacing FSMC with NAND memories
Signed-off-by: Vipin <vipin.kumar@st.com>
SPEAr SoCs contain a serial memory interface controller. This
controller is used to interface with spi based memories.
This patch adds the driver for this IP.
Signed-off-by: Vipin <vipin.kumar@st.com>
SPEAr Architecture support added. It contains the support for
following SPEAr blocks
- Timer
- System controller
- Misc registers
Signed-off-by: Vipin <vipin.kumar@st.com>
These are few files directly imported from Linux kernel source.
Those are not modifyed at all ar per strategy.
These files contains source with GPLv2 only
whereas u-boot expects GPLv2 or latter
These files are updated for the same from prior permission from original writes
Acked-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Because of v7_flush_dcache_all is moved to omap3/cache.S
and s5pc110 needs cache routines, update s5pc1xx cache routines.
l2_cache_enable and l2_caceh_disable are moved from cache.c to cache.S
and invalidate_dcache is modified for SoC specific.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control
for S3C6400. In the configuration of SMDK6400, however, two 16-bit
mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit
memory bus and there is no need to control CKE for each chip
separately. AFAIK, CKE1 is not at all connected. Only CKE0 is
used. Futhermore, it should be '0' always for S3C6410. When tested
with a board which has a S3C6410 and the same memory configuration,
a side effect is observed that u-boot command "reset" doesn't work
leading to system hang. Leaving the bit clear is safe in most cases.
Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Added DA8xx GPIO base addresses in gpio_defs.h and pointers
to different BANKs which can be used to program GPIOs.
Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Swaminathan S <swami.iyer@ti.com>
Davinci: NAND enable ECC even when not in NAND boot mode
On Davinci platforms, the default NAND device is enabled (for ECC)
in low level boot code when NAND boot mode is used. If booting in
another mode, NAND ECC is not enabled. The driver should make
sure ECC is enabled regardless of boot mode if NAND is configured
in U-Boot.
Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Davinci: Configurable NAND chip selects
Add a CONFIG_SYS_NAND_CS setting to all davinci configs and
use it to setup the NAND controller in the davinci_nand
mtd driver.
Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
This patch adds support for A320 evaluation board from Faraday. This board
uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM.
FA526 is an ARMv4 processor and uses the ARM920T source in this patch.
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
Defaults are for Infineon DDR timings.
Since none of the supported boards currently do
XIP boot, these seem to be faulty. fix the values
as per the calculations(ACTIMA,B), conf
the sdrc power with pwdnen and wakeupproc bits
Signed-off-by: Nishanth Menon <nm@ti.com>
Provides initial support for TI OMAP-L1x/DA8xx SoC devices.
See http://www.ti.com
The DA8xx devices are similar to DaVinci devices but have a differing
memory map and updated peripheral versions.
Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This patch adds a unified s3c24x0 cpu header file that selects the header
file for the specific s3c24x0 cpu from the SOC and CPU configs defined in
board config file. This removes the current chain of s3c24-type #ifdef's
from the s3c24x0 code.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Cleans up the s3c24x0 header files:
s4c24x0.h: removes the use of 'volatile' from the S3C24X0_REG8,
S3C24X0_REG16 and S3C24X0_REG32 register typedef's. Registers are always
accessed using the IO accessor functions which cast the register address
as 'volatile' anyway so it isn't required here.
s3c2400.h and s3c2410.h: insert a blank line between the static inline
functions
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
This patch moves the s3c24x0 header files from include/ to
include/asm-arm/arch-s3c24x0/.
checkpatch.pl showed 2 errors and 3 warnings. The 2 errors were both due
to a non-UTF8 character in David M?ller's name:
ERROR: Invalid UTF-8, patch and commit message should be encoded in UTF-8
#489: FILE: include/asm-arm/arch-s3c24x0/s3c2410.h:3:
+ * David M?ller ELSOFT AG Switzerland. d.mueller@elsoft.ch
As David's name correctly contains a non-UTF8 character I haven't fixed
these errors.
The 3 warnings were all because of the use of 'volatile' in s3c24x0.h:
WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt
#673: FILE: include/asm-arm/arch-s3c24x0/s3c24x0.h:35:
+typedef volatile u8 S3C24X0_REG8;
+typedef volatile u16 S3C24X0_REG16;
+typedef volatile u32 S3C24X0_REG32;
I'll fix these errors in another patch.
Tested by running MAKEALL for ARM8 targets and ensuring there were no new
errors or warnings.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add support to use second and third I2C bus, too.
Bus 0 is still the default, but by calling i2c_set_bus_num(1/2) before doing
I2C accesses, code can switch to bus 1 and 2, too. Don't forget to switch
back afterwards, then.
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
The asm-arm/unaligned.h includes linux/unaligned/access_ok.h
This file is unsafe to be used on ARM, since it does an unaligned memory
accesses which fails on ARM.
Lookin at Linux the basic difference seems to be the header
"include/asm-arm/unaligned.h". The Linux version of "unaligned.h"
does *not* include "access_ok.h" at all. It includes "le_byteshift.h"
and "be_byteshift.h" instead.
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Stefan Roese <sr@denx.de>
--
include/asm-arm/unaligned.h | 3 -
include/linux/unaligned/be_byteshift.h | 70 +++++++++++++++++++++++++++++++++
include/linux/unaligned/le_byteshift.h | 70 +++++++++++++++++++++++++++++++++
3 files changed, 142 insertions(+), 1 deletion(-)
create mode 100644 include/linux/unaligned/be_byteshift.h
create mode 100644 include/linux/unaligned/le_byteshift.h
fix the following compile warnings
warning: dereferencing type-punned pointer will break strict-aliasing rules
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Due to new TI boards being added to U-Boot, the hardware.h
is getting very messy. The warning being fixed is due to
the EMIF addresses being redefined.
The long term solution(after 2009.11) to this is to
have SOC specific header files.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
gpmc_config should not be a variant as it is board specific
hence make it a const parameter
Fixes issues identified by Dirk:
- build issue for zoom2
- warnings for all other OMAP3 platforms using nand/onenand etc
Signed-off-by: Nishanth Menon <nm@ti.com>
Export enable_gpmc_cs_config into common header to
prevent warning:
warning: implicit declaration of function 'enable_gpmc_cs_config'
Signed-off-by: Nishanth Menon <nm@ti.com>
This patch adds support for the Samsung s5pc100 and s5pc110
SoCs. The s5pc1xx SoC is an ARM Cortex A8 processor.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
Some DaVinci SOC's use GPIOs to enable EMAC and DM9000.
This patch adds some definitions for GPIO registers and also adds
structures for GPIO.
A separate header file is being added so that in future we
can have a DaVinci GPIO driver similer to OMAP.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Acked-by: Tom Rix <Tom.Rix@windriver.com>
In the DaVinci specific code, we use both CONFIG_SOC_DM646X and
CONFIG_SOC_DM646x to represent DM646x specific code.
This patch changes occurrences of CONFIG_SOC_DM646x to
CONFIG_SOC_DM646X. This is because for DM644x series of SOCs we use
the flag CONFIG_SOC_DM644X. We want some uniformity.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Acked-by: Tom Rix <Tom.Rix@windriver.com>
