The indirect write code is buggy pile of nastiness which fails horribly
when the system runs fast enough to saturate the controller. The failure
results in some pages (256B) not being written to the flash. This can be
observed on systems which run with Dcache enabled and L2 cache enabled,
like the Altera SoCFPGA.
This patch replaces the whole unmaintainable indirect write implementation
with the one from upcoming Linux CQSPI driver, which went through multiple
rounds of thorough review and testing. While this makes the patch look
terrifying and violates all best-practices of software development, all
the patch does is it plucks out duplicate ad-hoc code distributed across
the driver and replaces it with more compact code doing exactly the same
thing.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vignesh R <vigneshr@ti.com>
There could be runtime determined board specific reason why a EHCI
initialization fails (e.g. ENODEV if a Port is not available). In
this case, properly return the error code.
While at it, that function (board_ehci_hcd_init) has actually two
documentation blocks... Use the correct function name for the
documentation block of board_usb_phy_mode.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Tegra20's PCIe controller has a couple of quirks. There are workarounds in
the driver for these, but they don't work after the DM conversion:
1) The PCI_CLASS value is wrong in HW.
This is worked around in pci_tegra_read_config() by patching up the value
read from that register. Pre-DM, the PCIe core always read this via a
16-bit access to the 16-bit offset 0xa. With DM, 32-bit accesses are used,
so we need to check for offset 0x8 instead. Mask the offset value back to
32-bit alignment to make this work in all cases.
2) Accessing devices other than dev 1 causes a data abort.
Pre-DM, this was worked around in pci_skip_dev(), which the PCIe core code
called during enumeration while iterating over a bus. The DM PCIe core
doesn't use this function. Instead, enhance tegra_pcie_conf_address() to
validate the bdf being accessed, and refuse to access invalid devices.
Since pci_skip_dev() isn't used, delete it.
I've also validated that both these WARs are only needed for Tegra20, by
testing on Tegra30/Cardhu and Tegra124/Jetson TKx. So, compile them in
conditionally.
Fixes: e81ca88451 ("dm: tegra: pci: Convert tegra boards to driver model for PCI")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Memset pools_params as "0" to avoid garbage value in dpni_set_pools.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reported-by: Jose Rivera <german.rivera@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Initialize desc_before_addr, otherwise the USB core won't send the
first 64B Get Device Descriptor request in common/usb.c function
usb_setup_descriptor() . There are some USB devices which expect
this sequence and otherwise can misbehave.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Tom Rini <trini@konsulko.com>
Introduce a new flag in the controller private data, which allows selectively
disabling the OC protection. Use the standard 'disable-over-current' OF prop
to set this flag. This OC protection must be disabled on EBV SoCrates rev 1.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Introduce a boolean flag in the dwc2 controller private data and set
it according to the macro (for now) instead of having this macro
directly in the dwc_otg_core_init(). This will let us configure the
flag from DT or such later on, if needed.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Pass the whole bulk of private data instead of just the regs,
since the private data will soon contain important configuration
flags.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
The DMA was outputting the palette on the screen because the base
for the DMA was not after the palette. In addition to that, the ceiling was
also too high, this led that the output on the screen was shifted.
NOTE: According to the TRM, even in 16/24bit mode a palette is required
in the first 32 bytes of the framebuffer.
See also:
https://e2e.ti.com/support/arm/sitara_arm/f/791/p/234967/834483#834483
"In this mode, the LCDC will assume all information is data and thus you
need to ensure that the DMA points to the first pixel of data and not the
first entry in the frame buffer which is the beginning of the 512 byte
palette."
Signed-off-by: Martin Pietryka <martin.pietryka@chello.at>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
To support 16bpp we just need to change the raster_ctrl register
accordingly. Also 32bpp mode should work as well, but was not tested.
According to the TRM the uppermost byte will be ignored when
LCD_TFT_24BPP_UNPACK is set.
The switch logic is based on the Linux kernel tilcdc driver:
drivers/gpu/drm/tilcdc/tilcdc_crtc.c: lines 407 through 419
(kernel was checked out at commit: bcc981e9ed8)
Signed-off-by: Martin Pietryka <martin.pietryka@chello.at>
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
According to the TRM you have to set bits [21:20] to 0b10 for RAW mode, so
(0x10 << 20) is obviously wrong here.
Signed-off-by: Martin Pietryka <martin.pietryka@chello.at>
The terminal condition in the area where a PCI device is scanned is wrong,
and 1f.7 isn't scanned.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This allows to drop annoying (char *) casts when setting the host
name of struct sdhci_host.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
get_timer() returns an unsigned 64-bit value, but is currently assigned to
a signed 32-bit variable. Due to sign extension and data truncation, this
causes the timeout loop in spi_flash_cmd_wait_ready() to immediately (and
incorrectly) fire for about 50% of all time values, based on whether bit
31 is set. In sandbox at least, this causes the test to pass or fail based
on system uptime, as opposed to time since the U-Boot binary was started.
Fixes: 4efad20a17 ("sf: Update status reg check in spi_flash_cmd_wait_ready")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
U-Boot typically interprets unprefixed numbers as base 16, and DFU RAM
entity parsing has historically done so. Reverse the change to default
to base 10, so that values in previously working command-lines aren't
mis-parsed, causing RAM corruption, crashes, hangs, etc.
Fixes: 6aeb877afef0 ("drivers: dfu: ram: fix a crash with dfu ram with invalid dfu_alt_info env")
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
[Test HW: AM335x BBB]
U-Boot crashes when an invalid dfu_alt_info is set and tried
using dfu command. Fixing this as it is handled in dfu-mmc.
=> dfu 0 ram 0
data abort
pc : [<9ff893d6>] lr : [<9ff6edb9>]
reloc pc : [<808323d6>] lr : [<80817db9>]
sp : 9ef36cf0 ip : 00000158 fp : 9ffbc0b8
r10: 9ffbc0b8 r9 : 9ef36ed8 r8 : 00000000
r7 : 00000000 r6 : 9ffbc0c8 r5 : 9ef36cfc r4 : 9ef392c8
r3 : 00000004 r2 : 00000000 r1 : 9ff9a985 r0 : ffffffff
Flags: Nzcv IRQs off FIQs on Mode SVC_32
Resetting CPU ...
resetting ...
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Remaining bytes means bytes that are not yet transferred
and not the bytes that were transferred in the last transfer.
Reported-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Tested-by: Steve Rae <srae@broadcom.com>
[Test HW: bcm28155_ap board]
Request size can be greater than ep.packet and still end in a
short packet. We need to tackle this case as end of transfer
(if short_not_ok is not set) as indicated in USB 2.0 Specification [1],
else we get stuck up on certain protocols like fastboot.
[1] - USB2.0 Specification, Section 5.3.2 Pipes
Reported-by: Steve Rae <steve.rae@broadcom.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Tested-by: Steve Rae <steve.rae@broadcom.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Just use ep->maxpacket to get the maxpacket size
and simplify the bulk-out maxpacket alignment.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Tested-by: Steve Rae <srae@broadcom.com>
In a dual speed configuration we need to check at runtime if
we want to enable the Full-Speed or High-Speed endpoint.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Steve Rae <srae@broadcom.com>
[Test HW: bcm235xx board]
wMaxPacketSize for IN endpoing in High-Speed must be 512 and not 64.
While fixing that we do some clean ups like
- use cpu_to_le16(decimal_length) instead of hexadecimal length.
- No need to initialize bInterval to 0. Static variables are 0 initialized.
- Move descriptor setting from fastboot_add to to fastboot_bind.
- check for dual speed configuration before setting the high speed descriptors.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Tested-by: Steve Rae <srae@broadcom.com>
Tested-by: Steve Rae <srae@broadcom.com> [Test HW: bcm235xx board]
This patch adds support for the PCI(e) based I2C cores. Which can be
found for example on the Intel Bay Trail SoC. It has 7 I2C controllers
implemented as PCI devices.
This patch also adds the fixed values for the timing registers for
BayTrail which are taken from the Linux designware I2C driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This patch adds DM support to the designware I2C driver. It currently
supports DM and the legacy I2C support. The legacy support should be
removed, once all platforms using it have DM enabled.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
This patch prepares the designware I2C driver for the DM conversion.
This is mainly done by removing struct i2c_adapter from the functions
that shall be used by the DM driver version as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Integrating set_speed() into dw_i2c_set_bus_speed() will make the
conversion to DM easier for this driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
dw_i2c_enable() is used to dis-/en-able the I2C controller. It makes
sense to add such a function, as the controller is dis-/en-abled
multiple times in the code. Additionally, this function now checks,
if the controller is really dis-/en-abled. This code is copied
from the Linux I2C driver version.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add the ic_enable_status register to the i2c_regs struct. Additionally
the register offsets are added, to better check, if the offset matches
the register description in the datasheet.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
On some platforms (e.g. x86), the return value of dev_get_addr() can't
be assigned to a pointer type variable directly. As there might be a
difference between the size of fdt_addr_t and the pointer type. On
x86 for example, "fdt_addr_t" is 64bit but "void *" only 32bit. So
assigning the register base directly in dev_get_addr() results in this
compilation warning:
warning: cast to pointer from integer of different size
This patch introduces the new function dev_get_addr_ptr() that
returns a pointer to the 'reg' address that can be used by drivers
in this case.
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
I found many mistakes in the initial version.
Fixes: 8a3328c209 ("pinctrl: uniphier: support UniPhier PH1-LD20 pinctrl driver")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Set free_count to zero before walking through ai->erase list
in wl_init().
As U-Boot has no workqueue/threads, it immediately calls
erase_worker(), which increase for each erased block
free_count. Without this patch, free_count gets after
this initialized to zero in wl_init(), so the free_count
variable always has the maybe wrong value 0.
Detected this behaviour on the dxr2 board, where the
UBI fastmap gets not written when attaching/dettaching
on an empty NAND. It drops instead the error message:
could not find any anchor PEB
With this patch, fastmap gets written on dettach.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
While at it, remove obsolete CONFIG_USBDOWNLOAD_GADGET option from some
config headers. This is also probably fixes am335x_baltos board.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Move CONFIG_USB_GADGET_DUALSPEED option to Kconfig and
make all UDC controllers select USB_GADGET_DUALSPEED:
- add next options to Kconfig selecting USB_GADGET_DUALSPEED:
- USB_GADGET_ATMEL_USBA
- USB_GADGET_DWC2_OTG
- USB_DWC3
- CI_UDC
- make USB_MUSB_GADGET select USB_GADGET_DUALSPEED
While at it, make some related fixes:
- remove DUALSPEED from configs that don't enable gadget support:
- kwb.h
- tseries.h
- add missing USB_GADGET option to next configs:
- novena_defconfig
- pcm051_rev*_defconfig
- xfi3_defconfig
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
The description was borrowed from kernel. Definitions were added to
defconfig files in a way that "make savedefconfig" generates exactly
the same file as used defconfig.
Boards using 0 mA as CONFIG_USB_GADGET_VBUS_DRAW value were moved to use
2 mA (as minimal allowed by Kconfig).
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
The USB Mass Storage (ums) works in Windows, Linux and OS X (EL Capitan).
But, not in OS X (Yosemite). By applying the said patch, it extends
the ums support.
Signed-off-by: John Tobias <john.tobias.ph@gmail.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Test HW: Odroid XU3 (./test/py UMS + DFU tests)
Tested-by: John Tobias <john.tobias.ph@gmail.com>
Linux:
- Run ums to expose all my eMMC partition - shows all correctly
- Run ums to expose only 1 partition of my eMMC - show correctly
Windows:
- Run ums to expose all my eMMC partition - it detects but it prompts,
if I want to format it (due to a non windows partition)
- Run ums to expose only the FAT32 partition - it show the partition
correctly.
The code uses a lot of signed numbers, which ended up in variables
of unsigned type, which resulted in all sorts of underflows. This
in turn caused incorrect calibration on certain boards. Moreover,
repair the readout of the DQ delay, which was being pulled from
wrong register.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Just staticize global variables in sequencer, since there is no
point in having these symbols available outside of the DDR code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Originally, the DLEVEL selects the debug level within the sequencer code,
but only displays the messages on that particular debug level. Tweak the
handling such that for particular debug level, debug messages on that
level and lower are displayed. This allows better regulation of debug
message verbosity.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
This one last set of delay configuration registers was not properly
zeroed out originally, fix it and zero them out.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
There is no point in resetting the ODT setting if the write test
failed, since the code will always retry the calibration and thus
reconfigure the ODT anyway OR the code will fail calibration and
halt.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Every invocation of the scc_mgr_set_dqs_en_delay_all_ranks() is
followed by SCC manager update. Moreover, only this function
triggers the SCC manager update internally. Thus, remove the
internal invocation to avoid triggering the update twice.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
The hi address bitfield in the protection rule must be set to
the last address in the region which the rule represents. The
behavior is now in-line with code generated by Quartus 15.1 .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
The code should be setting registers to zero, not one register to value.
Swap the order of arguments to correct the behavior. The behavior is now
in-line with code generated by Quartus 15.1 .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
In the most unlikely case the DQS tracking was to be disabled,
make sure we do not errornously re-enable it. Note that DQS
tracking is enabled on all systems observed thus far.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
The bit 22 is in fact DQS tracking enable bit (dqstrken) and there
is a macro for this bit already, so use it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
Ensure data the following sata command used is flushed out of dcache
and written to physical memory or timeout error may happen.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
dm_serial_ops.pending should return the number of characters, not just a
valid C Boolean integer value. The existing code does already does this,
but only as an accident since BCM283X_MU_LSR_RX_READY happens to be
BIT(0). Enhance the code to be more explicit about the values it returns.
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Not all Keystone2 devices has AEMIF NAND controller. So adding Kconfig
entry for CONFIG_TI_AEMIF and enabling it in respective defconfigs on
platforms with AEMIF controller.
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
If get_dev_addr fails it will return FDT_ADDR_T_NONE and:
>>> "priv->usid == 4294967295U" is always false regardless of the values of its operands. This occurs as the logical operand of if.
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reported-by: Coverity (CID: 143914)
Signed-off-by: Tom Rini <trini@konsulko.com>
If get_dev_addr fails it will return FDT_ADDR_T_NONE and:
>>> "priv->pid == 4294967295U" is always false regardless of the values of its operands. This occurs as the logical operand of if.
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Reported-by: Coverity (CID: 143913)
Signed-off-by: Tom Rini <trini@konsulko.com>
Add request gpio for CD and WP gpios, so that the gpio can be
used for the respective purposes.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
omap_hsmmc driver directly typecasts fdt_addr_t to a pointer.
This is not strictly correct, as it gives a build warning when
fdt_addr_t is u64. So, use map_physmem for a proper typecasts.
This is inspired by commit 167efe01bc ("dm: ns16550: Use an address
instead of a pointer for the uart base")
drivers/mmc/omap_hsmmc.c: In function ‘omap_hsmmc_ofdata_to_platdata’:
drivers/mmc/omap_hsmmc.c:776:20: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
priv->base_addr = (struct hsmmc *)dev_get_addr(dev);
^
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
In rollback_space_kernel we were not initializing the reserved fields
which should be for safety sake, and doing memset here means we don't
need to set the version field specifically either.
Reported-by: Coverity (CID: 143917)
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
This function parses the reg property based on an index found in the
reg-names property. This is required for bindings that are written
using reg-names rather than hard-coding indices in reg.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fix multi-line comment indentation in device_bind()
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We may have pinmux settings for pinctrl device, like the following
example:
"
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_1>;
imx6ul-evk {
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000
>;
};
[......]
};
"
We should not only select pinctrl state for non pinctrl devices, we
need also to handle pin mux settings such as pinctrl_log for pinctrl
devices.
So at the end of probing process of pinctrl device, select the default
state of pinctrl device.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This is a possible drop in replacement for drivers/i2c/zynq-i2c.c
Since this is cadence IP it has been renamed to cdns-i2c,
to make sense with the compatible string.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Warnings:
w+../drivers/gpio/pca953x.c: In function ‘do_pca953x’:
w+../drivers/gpio/pca953x.c:220:5: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
w+../drivers/gpio/pca953x.c:233:10: warning: cast from pointer to
integer of different size [-Wpointer-to-int-cast]
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Enable ZYNQ_GPIO for ZynqMP using Kconfig. It enables the GPIO
driver support for ZynqMP.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Move all the gpio definitions to driver file as
there is no use of them in other files.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove non driver model support as it moved
to driver model. Dont need non driver model
anymore.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Enable DM GPIO and ZYNQ GPIO using kconfig instead of the board
config file.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Unlock current sector instead of sector 0 before buffered write.
[Patch subject and commit text slightly reworded, Stefan]
Signed-off-by: Rouven Behr <u-boot@behr-iss.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds the missing configuration of the output value to the
gpio_direction_output() function. Without this, calling
gpio_direction_output() does not set the out-value at all and only
configures the gpio as output.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Reviewed-by: Kevin Smith <kevin.smith@elecsyscorp.com>
On the H3 we need to enable the clk and de-assert the reset of the
companion to be able to talk to the actual usb host controller.
Before this commit we were also disabling the companion clk-gate /
asserting its reset on remove, causing the later remove callback of
the companion itself to (sometimes) fail with:
ERROR: USB HC reset timed out!
This commit fixes this by not disabling the companion's clk-gate nor
asserting its reset on remove.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
To make the usage of this function more flexible, lets add the CRC start
value as parameter to this function. This way it can be used by other
functions requiring different start values than 0 as well.
For non-zero CRC start values to work, I've reworked the function a bit.
The new implementation is copied from the Linux version in
drivers/i2c/i2c-core.c / i2c_smbus_pec(). Which supports non-zero
CRC stating values.
I've double-checked that the results for zero starting values are
identical to the results from the original version of this function.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch adds a call to flush_dcache_range() to bootcount_store() to
make sure, that the bootcounter data (including the patterns) is
written to memory. Without this, platforms with dcache enabled may not
have the bootcounter updated upon reset.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
After writing data to flash space, next instruction is checking if flash
controller is busy writing to the flash memory. Memory barrier is required here
to avoid transaction re-ordering for data write and busy status check.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
There is off-by-one error in sandbox_emul_gpio that causes
segfault of certain tests.
EMUL_GPIO_REG_END is the address of last valid (emulated) register.
This patch fixed this (by adding one more element to emulated register array).
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
ISS is obsolete now and nSIM is used for simulation instead.
In its turn nSIM properly handles baud-rate settings so get rid
of now useless check.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
The dwmmc.h include was forgotten during the migration of dwmmc
probing to DM. Since the shiny DM is in place now, remove this
relic of the past.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
musb_lowlevelinit(): if no device is plugged in / detected call
musb_stop() to undo the preceding musb_start() call.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The probe function of the musb host driver can be called multiple
times. The code assumes that it can save the pointer to the allocated
musb struct in the driver model priv_auto_alloc data, but this data
gets free-ed on a probe failure or on removal, so we must save the
pointer elsewhere.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Changes the return type of fdt_usb_get_node_type from char* to int
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Move usb device-tree fixup framework from ehci-fsl.c to common place so
that it can be used by other drivers as well (xhci-fsl.c).
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Acked-by: Marek Vasut <marex@denx.de>
This commit fixes crash on BananaPi (and possibly others)
casued by 3f9f8a5b83.
Crash reason:
When no ops were passed to ehci_register(), USB host driver caused
NULL pointer dereference.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
This driver adds support of PIC32 MUSB OTG controller as dual role device.
It implements platform specific glue to reuse musb core.
Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Definition of writes{bwlq}, reads{bwlq} are now added into arch specific
asm/io.h. So removing them from driver to fix re-definition error
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
