Get the start and end address for clearing BSS from the newly
introduced symbols __bss_start and __bss_end. After GOT is
relocated, those symbols are already pointing to the correct
addresses.
Also optimize the loop by moving the address incrementation
to the delay slot to avoid the initial sub instruction.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The difference between the address of the original
and the relocated _GLOBAL_OFFSET_TABLE_ is always
the same as the relocation offset.
The relocation offset is already computed and it is
available in the 's1/t6' register. Use that to adjust
the relocated _G_O_T_ address, instead of calculating
the offset again from the _gp value.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
Saving the parameters in advance unnecessarily complicates
the code. The destination address is already saved in the
's2' register, and that register is not clobbered by the
copy loop. The size of the copied data can be computed
after the copy loop is done.
Change the code to compute the size parameter right
before calling flush_cache, and set the destination
address parameter in the delay slot of the actuall
call.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
The current code uses four instructions and a
temporary register to calculate the relocation
offset and to adjust the gp register.
The relocation offset can be calculated directly
from the CONFIG_SYS_MONITOR_BASE constant and from
the destination address. The resulting offset can
be used to adjust the gp pointer.
This approach makes the code a bit simpler because
it needs two instructions only.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Save the reused parameters at the beginning
of the 'relocate_code' function. This makes
the function a bit more readable.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
The current code uses two instructions to load
the stack pointer into the 'sp' register.
This results in the following assembly code:
468: 3c088040 lui t0,0x8040
46c: 251d0000 addiu sp,t0,0
The first instuction loads the stack pointer into
the 't0' register then the value of the 'sp' register
is computed by adding zero to the value of the 't0'
register. The same issue present on the 64-bit version
as well:
56c: 3c0c8040 lui t0,0x8040
570: 659d0000 daddiu sp,t0,0
Change the code to load the stack pointer directly
into the 'sp' register. The generated code is functionally
equivalent to the previous version but it is simpler.
32-bit:
468: 3c1d8040 lui sp,0x8040
64-bit:
56c: 3c1d8040 lui sp,0x8040
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
The loop code copies more data with one than
necessary due to the 'ble' instuction. Use the
'blt' instruction instead to fix that.
Due to the lack of suitable hardware the Xburst
specific code is compile tested only. However the
change is quite obvious.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
The romReserved and romExcHandle handlers are
accessed by a branch instruction however the
delay slots of those instructions are not filled.
Because the start.S uses the 'noreorder' directive,
the assembler will not fill the delay slots either,
and leads to the following assembly code:
0000056c <romReserved>:
56c: 1000ffff b 56c <romReserved>
00000570 <romExcHandle>:
570: 1000ffff b 570 <romExcHandle>
In the resulting code, the second branch instruction
is placed into the delay slot of the first branch
instruction, which is not allowed on the MIPS
architecture.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Currently the cache operation mode is hard-coded to
CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs
which operate at a different mode.
This patch makes the cache operation mode configurable via board config.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Acked-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
This define is a board-specific config option and should be
renamed to follow the U-Boot naming convention. Additionally,
add an explaining comment for this option.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Acked-by: Thomas Langer <thomas.langer@lantiq.com>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Fix style issues and alignments globally. No logical changes.
- Replace C comments with AS line comments where possible
- Use ifndef where possible, rather than if !defined for simplicity
- An instruction executed in a delay slot is now indicated by a leading
space, not by C comment
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
As requested in commit e1390801a3 ([MIPS]
Request for the 'mips_cache_lock()' removal), such feature is no longer
needed for current MIPS implementation of U-Boot, and no one in the tree
uses it for years.
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
All current CPUs and SoCs are based on MIPS32 arch. The complete
code resides in the global arch/mips/cpu directory. This is not
suitable if other MIPS architectures like MIPS64 or Octeon should
be supported in the future.
To achieve this the current CPU code is moved to its own mips32
subdirectory. All MIPS32 boards have to use mips32 as config switch
in board.cfg.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Thomas Lange <thomas@corelatus.se>
Cc: Vlad Lungu <vlad.lungu@windriver.com>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
