Commit Graph

27060 Commits

Author SHA1 Message Date
Ye.Li
e3568d2eca DM: thermal: Add imx thermal DM driver
Add a new thermal uclass for thermal sensor and implement the imx
thermal driver basing on this uclass.

Signed-off-by: Ye.Li <B37916@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-11-21 15:30:01 +01:00
Nitin Garg
cf202d268b mx6: clock: Add thermal clock enable function
Add api to check and enable pll3 as required
for thermal sensor driver.

Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
2014-11-21 15:18:47 +01:00
Soeren Moch
02a32a92d4 tbs2910: Fix error handling in board_mmc_init()
When an invalid USDHC port is passed we should return -EINVAL instead of 0.
Also, return the error immediately on fsl_esdhc_initialize() failure.

Based on similar patches by Fabio Estevam for mx6sabresd, mx53loco, wandboard

Signed-off-by: Soeren Moch <smoch@web.de>
Acked-by: Stefano Babic <sbabic@denx.de>
2014-11-21 15:16:18 +01:00
Simon Glass
c1a6f371ae dm: i2c: Move error reporting into a common function
Factor out the common code to make it easier to adjust it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
2014-11-21 08:14:54 +01:00
Simon Glass
38687ae676 dm: Update documentation to include CONFIG_DM... options
Add documentation for the various driver model options that are now
available.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:14:27 +01:00
Simon Glass
f8fff9dac9 dm: arm: spl: Make driver model linker lists available
The linker lists feature is useful in SPL as it holds the driver model
platform data. So don't throw away the lists.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
2014-11-21 08:14:11 +01:00
Simon Glass
0521f98427 dm: tegra: Add platform data for the GPIO driver
Add platform data for the GPIO driver. It doesn't need to contain anything
since the GPIO driver will actually use information from the CONFIGs for
now. This merely serves to ensure that the GPIO driver is bound.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:14:07 +01:00
Simon Glass
bc0b28427a dm: tegra: Add platform data for the SPL uart
Since we currently don't have device tree available in SPL, add platform
data so the uart works.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:14:02 +01:00
Simon Glass
a94f468fa2 dm: Disable dm_warn() in SPL
Since this function can use up quite a bit of space for its strings, disable
it by default in SPL. Use CONFIG_DM_WARN to re-enable it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
2014-11-21 08:13:17 +01:00
Simon Glass
236f2bd302 dm: Allow stdio registration to be dropped
Provide a CONFIG_DM_STDIO option to enable registering a serial device
with the stdio library. This is seldom useful in SPL, so disable it by
default when building for SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
2014-11-21 08:13:14 +01:00
Simon Glass
3ac435d33a dm: Allow device removal features to be dropped
For SPL we don't expect to need to remove a device. Save some code space
by dropping this feature. The board config can define
CONFIG_DM_DEVICE_REMOVE if this is in fact needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@ti.com>
2014-11-21 08:13:02 +01:00
Simon Glass
1151651831 dm: spl: Allow driver model to be used
When enabled, set up driver model for SPL. This allows SPL to use the same
drivers as the main U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Tom Rini <trini@ti.com>
2014-11-21 08:12:55 +01:00
Simon Glass
fb4f5e7c91 dm: spl: Make simple malloc() available when enabled
Set up the simple malloc() implementation when requested, in preference to
the full malloc().

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:12:52 +01:00
Simon Glass
ba19599b44 dm: arm: spl: Allow simple malloc() in SPL
For SPL it is sometimes useful to have a simple malloc() just to permit
driver model to work, in the cases where the full malloc() is not made
available by the board config.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:12:39 +01:00
Simon Glass
c9356be307 dm: Split the simple malloc() implementation into its own file
The simple malloc() implementation is used when memory is tight. It provides
a simple buffer with an incrementing pointer.

At present the implementation is inside dlmalloc. Move it into its own file
so that it is easier to find.

Rather than using relocation as a signal that the full malloc() is
available, add a special GD_FLG_FULL_MALLOC_INIT flag. This signals that the
simple malloc() should no longer be used.

In some cases, such as SPL, even the code space used by the full malloc() is
wasteful. Add a CONFIG_SYS_MALLOC_SIMPLE option to provide only the simple
malloc. In this case the full malloc is not available at all. It saves about
1KB of code space and about 0.5KB of data on Thumb 2.

Acked-by: Tom Rini <trini@ti.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:12:28 +01:00
Simon Glass
9dacbb2772 dm: tegra: Avoid using arch-specific memcpy() in SPL
The faster functions are not actually available in SPL and the code size
likely isn't worth it. Use the normal memcpy() in SPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:11:13 +01:00
Simon Glass
ad1b81c880 dm: serial: Support changing the baud rate
Implement this feature in the uclass so that the baudrate can be changed
with 'setenv baudrate <rate>'.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:10:16 +01:00
Simon Glass
e87e0e79ed dm: at91: Add myself as maintainer for snapper9260
The old maintainer has left, so take this over.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:10:13 +01:00
Simon Glass
1a1927f3a3 dm: at91: Convert snapper9260 to use driver model
Convert this at91sam9260-based board to use driver model. This should serve
as an example for other similar boards. Serial and GPIO are supported so
far.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-11-21 08:10:03 +01:00
Simon Glass
0f65f48b64 dm: at91: Add driver model support for the serial driver
Add driver model support while retaining the existing legacy code. This
allows the driver to support boards that have converted to driver model
as well as those that have not.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:09:58 +01:00
Simon Glass
62137fc0ab dm: at91: Refactor serial driver slightly for driver model
Before adding driver model support, split out a few of the functions so
that they can be used by the driver model code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-11-21 08:09:55 +01:00
Simon Glass
12fe7f7c2a dm: at91: Add platform data for GPIO on at91sam9260-based boards
These boards all have the same GPIO arrangement, so add some common platform
data that can be used by all boards. Remove the configs which are no longer
required.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:09:36 +01:00
Simon Glass
918354b18e dm: at91: Add driver model support for atmel GPIO driver
Modify this driver to support driver model, with platform data required to
determine the GPIOs that it controls.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:08:19 +01:00
Simon Glass
cd052cd935 dm: at91: Move snapper9260 to generic baord
This works correctly, so switch it over before the deadline.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:08:16 +01:00
Simon Glass
5e8a749c28 dm: at91: Correct text base for snapper9260
The value should be 0x21f00000. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 08:08:07 +01:00
Simon Glass
fe5b9b447c x86: Rename chromebook-x86 to coreboot
Rename this vendor since it is intended to be used on any platform where
coreboot runs at reset and then loads U-Boot.

So far it is only tested on link. When other boards are supported it is
likely that we will need to move to multiple board names, all under the
'coreboot' vendor. So while it would be possible to remove the vendor for
now, that would be short-sighted.

Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:16 +01:00
Simon Glass
65dd74a674 x86: ivybridge: Implement SDRAM init
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree. This
also needs the Intel Management Engine (me.bin) to work. Binary blobs
everywhere: so far we have MRC, ME and microcode.

SDRAM init works by setting up various parameters and calling the MRC. This
in turn does some sort of magic to work out how much memory there is and
the timing parameters to use. It also sets up the DRAM controllers. When
the MRC returns, we use the information it provides to map out the
available memory in U-Boot.

U-Boot normally moves itself to the top of RAM. On x86 the RAM is not
generally contiguous, and anyway some RAM may be above 4GB which doesn't
work in 32-bit mode. So we relocate to the top of the largest block of
RAM we can find below 4GB. Memory above 4GB is accessible with special
functions (see physmem).

It would be possible to build U-Boot in 64-bit mode but this wouldn't
necessarily provide any more memory, since the largest block is often below
4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large
ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit
kernels directly so this does not pose a limitation in that area. Also there
are probably parts of U-Boot that will not work correctly in 64-bit mode.
The MRC is one.

There is some work remaining in this area. Since memory init is very slow
(over 500ms) it is possible to save the parameters in SPI flash to speed it
up next time. Suspend/resume support is not fully implemented, or at least
it is not efficient.

With this patch, link boots to a prompt.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
3eafce0527 x86: ivybridge: Add LAPIC support
The local advanced programmable interrupt controller is not used much in
U-Boot but we do need to set it up. Add basic support for this, which will
be extended as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
a49e3c7f09 x86: Make show_boot_progress() common
This function can probably be used on all x86 boards, so move it into the
common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
437c2b7cd0 x86: chromebook_link: Enable GPIO support
Enable GPIO support and provide the required GPIO setup information to
the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
1b4f25ff8e x86: ivybridge: Add support for early GPIO init
When not relying on Coreboot for GPIO init the GPIOs must be set up
correctly. This is currently done statically through a rather ugly method.
As the GPIOs are figured out they can be moved to the device tree and set
up as needed rather than all at the start.

In this implementation, board files should call ich_gpio_set_gpio_map()
before the GPIO driver is used in order to provide the GPIO information.
We use the early PCI interface so that this driver can now be used before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
8e0df066ff x86: ivybridge: Add early init for PCH devices
Many PCH devices are hard-coded to a particular PCI address. Set these
up early in case they are needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
9c678e152a x86: dts: Add microcode updates for ivybridge CPU
Add two microcode updates that are provided for this CPU. The updates
have been converted to a device tree form.

Note: SPDX submission has been done. If this license is approved I will
convert the files to use SPDX.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
77f9b1fb62 x86: ivybridge: Perform Intel microcode update on boot
Microcode updates are stored in the device tree. Work through these and
apply any that are needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
94060ff278 x86: ivybridge: Check BIST value on boot
The built-in self test value should be checked before we continue booting.
Refuse to continue if there is something wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:14 +01:00
Simon Glass
f5fbbe9579 x86: ivybridge: Perform initial CPU setup
Set up the flex ratio (controls speed versus heat output) and a few other
very early things.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:13 +01:00
Simon Glass
eddbad224b x86: Add msr read/write functions that use a structure
It is convenient to be able to adjust MSRs with a structure that splits the
two 32-bit halves into separate fields, as they are often dealt with
separately. Add a few functions to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:13 +01:00
Simon Glass
3f70a6f577 x86: Add clr/setbits functions
These are available on other architectures. Make them available on x86 also.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:13 +01:00
Simon Glass
378a8634ad x86: Tidy up coreboot header usage
There is no need to explicitly write 'arch-coreboot' when including headers,
as when the arch directory points to coreboot the correct files will be
used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:13 +01:00
Simon Glass
2b6051541b x86: ivybridge: Add early LPC init so that serial works
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:12 +01:00
Simon Glass
6fb3b72e87 x86: pci: Allow configuration before relocation
Add simple PCI access routines for x86 which permit use before relocation.
The normal PCI stack is still used, but for pre-relocation use there can
only ever be a single hose. After relocation, fall back to the normal
access, although even then on x86 machines there is normally only a single
PCI bus.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:12 +01:00
Simon Glass
6e5b12b614 x86: ivybridge: Enable PCI in early init
Enable PCI so we can access devices that need to be set up before relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:12 +01:00
Simon Glass
7430f10864 x86: Support use of PCI before relocation
Add support for using PCI before SDRAM is available, using early malloc()
and global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:34:12 +01:00
Simon Glass
d188b18f65 x86: Refactor PCI to permit alternate init
We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use early malloc() to store information about a PCI hose.

Common PCI code moves to arch/x86/cpu/pci.c and a new
board_pci_setup_hose() function is provided by boards to set up the (single)
hose used by that board.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:34:11 +01:00
Simon Glass
70a09c6c3d x86: chromebook_link: Implement CAR support (cache as RAM)
Add support for CAR so that we have memory to use prior to DRAM init.
On link there is a total of 128KB of CAR available, although some is
used for the memory reference code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:11 +01:00
Simon Glass
d1cd045982 x86: Emit post codes in startup code for Chromebooks
On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
see where the code got to before it died.

On modern hardware these codes are not normally visible. On Chromebooks
they are displayed by the Embedded Controller (EC), so it is useful to emit
them. We must enable this feature for the EC to see the codes, so add an
option for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:34:11 +01:00
Simon Glass
fce7b27683 x86: Build a .rom file which can be flashed to an x86 machine
On x86 machines U-Boot needs to be added to a large ROM image which is
then flashed onto the target board. The ROM has a particular format so it
makes sense for U-Boot to build this image automatically. Unfortunately
it relies on binary blobs so we cannot require this for the default
build as yet.

Create a u-boot.rom output file for this purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:11 +01:00
Simon Glass
8ef07571a0 x86: Add chromebook_link board
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.

This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:11 +01:00
Simon Glass
c03c951b06 x86: ifdtool: Allow creation of an empty ROM
Allow an empty ROM to be created, without needing to provide a descriptor.
The descriptor is not needed on some x86 boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:05 +01:00
Simon Glass
5c1b685e46 x86: Allow timer calibration to work on ivybridge
Unfortunately MSR_FSB_FREQ is not available on this CPU, and the PIT method
seems to take up to 50ms which is much too long.

For this CPU we know the frequency, so add another special case for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:12 +01:00