The LCDC IP-core an be feed from several clock sources, one of those is
a dedicated DPLL for generating a dividable base-clock for this IP-core.
The TRM specifies the maximum input frequency for the LCCD with 200 MHz,
so we must not exceed this value with the PLL frequency (which can lock
much higher).
This patch tries every combination of multipliers and divisors of the
PLL and the IP-core itself for getting as near as possible the the
requested panel->pxl_clk.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Since i've been married, i also have a new surname.
Mr. Petermaier moved to Mr. Schmelzer.
In this patch i update all files in which my (old) name is present.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Often on boards exists a circuit which switches power on/off to LCD display.
Due to the need of limiting the in-rush current the output voltage from this
circuit rises "slowly", so it is necessary to wait a bit (VCC ramp up time)
before starting output on LCD-pins.
This time is specified in <n> ms within the panel-settings, called "pup_delay"
Further some LCDs need a couple of frames to stabilize the image on it.
We have now the possibility to wait some time after starting output on LCD.
This time is also specified in <n> ms within panel-settings, called "pon_delay"
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
- Adds support for a minimal framebuffer driver of TI's AM335x SoC
to be compatible with Wolfgang Denk's LCD-Framework (CONFIG_LCD,
common/lcd.c)
Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
