Commit Graph

339 Commits

Author SHA1 Message Date
Kouei Abe
1815c29738 gpio: rcar_gen3: Fix GPIO read support
This patch fixes to read the GPIO status after confirming the
INOUT setting.

Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Tom Rini <trini@konsulko.com>
2017-05-22 04:37:30 +09:00
Peng Fan
aab203eb2e gpio: 74x164: make oe-pins optional
Make oe-pins optional because some boards have fixed it to enable.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-18 11:24:34 +02:00
Bin Meng
770ee01742 x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode
Add a device-tree property use-lvl-write-cache that will cause
writes to lvl to be cached instead of read from lvl before each
write. This is required on some platforms that have the register
implemented as dual read/write (such as Baytrail).

Prior to this fix the blue USB port on the Minnowboard Max was
unusable since USB_HOST_EN0 was set high then immediately set
low when USB_HOST_EN1 was written.

This also resolves the 'gpio clear | set' command warning like:
  "Warning: value of pin is still 0"

Signed-off-by: George McCollister <george.mccollister@gmail.com>
<rebased on latest origin/master, fixed all baytrail boards>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-17 17:13:06 +08:00
Tom Rini
29cb2b3b90 gpio: Move OMAP_GPIO to Kconfig
This driver is used often enough such that we want to have this enabled
by default on any ARCH_OMAP2PLUS board, and this only compiles on
ARCH_OMAP2PLUS due to required defines, so mark that as the depends.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-15 10:40:00 -04:00
Tom Rini
758979101d gpio-uclass.c: Fix comparison of unsigned expression warning
We declare that gpio_base (which is the base for counting gpios, not an
address) is unsigned.  Therefore the comparison with >= 0 is always
true.  As the desire is to allow for this base number to be 0, we can
just drop this check.  Reported by clang-3.8.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-12 08:37:39 -04:00
Álvaro Fernández Rojas
e64bdb2fcf dm: gpio: add BCM6345 gpio driver
This driver is based on linux/arch/mips/bcm63xx/gpio.c, simplified to allow
defining one or two independent banks for each Broadcom SoC.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-10 16:16:09 +02:00
Vikas Manocha
774171020b dm: gpio: Add driver for stm32f7 gpio controller
This patch adds gpio driver supporting driver model for stm32f7 gpio.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Christophe KERELLO <christophe.kerello@st.com>
[trini: Add depends on STM32]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-08 11:57:02 -04:00
Chen-Yu Tsai
33559ffe5b gpio: sunxi: Add compatible string for R40 PIO
The PIO on the R40 SoC is mostly compatible with the A20.
Only a few pin functions for mmc2 were added to the PC
pingroup, to support 8 bit eMMCs.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2017-04-20 13:30:01 +02:00
Wenyou Yang
f2f3c1576a gpio: at91_gpio: add the clock support
Add the clock support.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2017-04-13 14:44:50 -06:00
Wenyou Yang
cf468880c3 gpio: at91_gpio: add the device tree support
Add the device tree support.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2017-04-13 14:44:50 -06:00
Wenyou Yang
5a07a5f922 gpio: Kconfig: add CONFIG_AT91_GPIO option
The CONFIG_AT91_GPIO option is used to select AT91 PIO GPIO driver.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2017-04-13 14:44:50 -06:00
Wenyou Yang
2dc63f7367 gpio: at91_gpio: remove CPU_HAS_PIO3 macro
The intention of the removal is the preparation to introduce the
new AT91 PIO pinctrl driver.

Use the union to make the PIO3 and PIO2's registers be together
and make their offset aligned.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-04-13 14:44:50 -06:00
Peng Fan
d665eb6114 gpio: Add Rapid GPIO2P driver for i.MX7ULP
Add the imx_rgpio2p driver for Rapid GPIO2P controllers on i.MX7ULP.
Have added all ports on RGPIO2P_0 and RGPIO2P_1.

The configurations CONFIG_IMX_RGPIO2P and CONFIG_DM_GPIO must be set
to y to enable the drivers.

To use the GPIO function, the IBE and OBE needs to set in IOMUXC.
We did not set the bits in driver, but leave them to IOMUXC settings
of the GPIO pins. User should use IMX_GPIO_NR to generate the GPIO number
for gpio APIs access.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by : Stefano Babic <sbabic@denx.de>
2017-03-17 09:27:08 +01:00
Tom Rini
21342d4aed Merge git://git.denx.de/u-boot-dm 2017-02-08 16:24:44 -05:00
Robert P. J. Day
7582ddce13 GPIO: Correct doc typo "confguration" -> "configuration"
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
2017-02-08 16:24:29 -05:00
Simon Glass
e160f7d430 dm: core: Replace of_offset with accessor
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-08 06:12:14 -07:00
Ajay Bhargav
c7c47ca246 Update Maintainer and Author's email address
I am not longer using my old email address
"ajay.bhargav@einfochips.com". For U-Boot development email address is
now updated to contact@8051projects.net

Signed-off-by: Ajay Bhargav <contact@8051projects.net>
2016-12-27 11:24:17 -05:00
Michal Simek
f2e70a0073 gpio: zynq: Remove empty line
Trivial coding style fix.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-12-20 09:15:27 +01:00
Fabian Vogt
4faf5f93c6 gpio: bcm2835: add device tree support
This patch adds device tree support for the bcm2835 GPIO driver.

Signed-off-by: Fabian Vogt <fvogt@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-11-28 20:09:45 -05:00
Phil Edworthy
2d0c2c47aa gpio: dwapb: Add support for port B
The IP supports two ports, A and B, each providing up to 32 gpios.
The driver already creates a 2nd gpio bank by reading the 2nd node
from DT, so this is quite a simple change to support the 2nd bank.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-11-21 14:07:26 -05:00
Wenyou Yang
d85d92ae7b gpio: atmel_pio4: Remove unnecessary clock calling
Due to the peripheral clock driver improvement, remove the
unnecessary clock calling.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
2016-10-28 18:37:14 +02:00
Simon Glass
b02e4044ff libfdt: Bring in upstream stringlist functions
These have now landed upstream. The naming is different and in one case the
function signature has changed. Update the code to match.

This applies the following upstream commits by
Thierry Reding <treding@nvidia.com> :

   604e61e fdt: Add functions to retrieve strings
   8702bd1 fdt: Add a function to get the index of a string
   2218387 fdt: Add a function to count strings

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-10-13 13:54:10 -06:00
Simon Glass
26f50fbed2 Revert "x86: broadwell: gpio: Remove the codes to set up pin control"
This makes the assumption that setting up pinctrl in cpu_init_r() is safe.
On samus we need GPIOs before relocation in order to support power control.
This commit fixes the following message on boot:

   initcall sequence ffe5c6f4 failed at call ffe01d3d (err=-1)
   ### ERROR ### Please RESET the board ###

In any case it seems better to leave init to driver model, so that it can
pick up the GPIO driver when it needs it. Since pinctrl is a dependency of
the GPIO driver, we may as well put the dependency there and avoid these
problems.

This reverts commit 9769e05bcf.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-11 11:55:33 +08:00
Masahiro Yamada
1221ce459d treewide: replace #include <asm/errno.h> with <linux/errno.h>
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content.  (both just wrap <asm-generic/errno.h>)

Replace all include directives for <asm/errno.h> with <linux/errno.h>.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-09-23 17:55:42 -04:00
Alexander Graf
601147b06a serial: bcm283x_mu: Detect disabled serial device
On the raspberry pi, you can disable the serial port to gain dynamic frequency
scaling which can get handy at times.

However, in such a configuration the serial controller gets its rx queue filled
up with zero bytes which then happily get transmitted on to whoever calls
getc() today.

This patch adds detection logic for that case by checking whether the RX pin is
mapped to GPIO15 and disables the mini uart if it is not mapped properly.

That way we can leave the driver enabled in the tree and can determine during
runtime whether serial is usable or not, having a single binary that allows for
uart and non-uart operation.

Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-09-06 13:18:19 -04:00
Alexander Graf
04a993fe11 bcm2835_gpio: Implement GPIOF_FUNC
So far we could only tell the gpio framework that a GPIO was mapped as input or
output, not as alternative function.

This patch adds support for determining whether a function is mapped as
alternative.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
2016-09-06 13:18:18 -04:00
Wenyou Yang
ee3311db1c gpio: atmel_pio4: Rework to support DM & DT
Rework the driver to support driver model and device tree, and
support to regard the pio4 pinctrl device as a child of
atmel_pio4 device.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-15 22:58:03 +02:00
Wenyou Yang
46ed9381b7 gpio: atmel_pio4: Move PIO4 definitions to head file
In order to make these PIO4 definitions shared with AT91 PIO4
pinctrl driver, move them from the existing gpio driver to the
head file, and rephrase them.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-15 22:58:03 +02:00
Stephen Warren
6e06acb732 fdt: allow fdtdec_get_addr_size_*() to translate addresses
Some code may want to read reg values from DT, but from nodes that aren't
associated with DM devices, so using dev_get_addr_index() isn't
appropriate. In this case, fdtdec_get_addr_size_*() are the functions to
use. However, "translation" (via the chain of ranges properties in parent
nodes) may still be desirable. Add a function parameter to request that,
and implement it. Update all call sites to default to the original
behaviour.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Squashed in build fix from Stephen:
Signed-off-by: Simon Glass <sjg@chromium.org>
2016-08-12 09:20:27 -06:00
Vignesh R
5746b0df9c gpio: Add driver for TI PCF8575 I2C GPIO expander
TI's PCF8575 is a 16-bit I2C GPIO expander.The device features a
16-bit quasi-bidirectional I/O ports. Each quasi-bidirectional I/O can
be used as an input or output without the use of a data-direction
control signal. The I/Os should be high before being used as inputs.
Read the device documentation for more details[1].

This driver is based on pcf857x driver available in Linux v4.7 kernel.
It supports basic reading and writing of gpio pins.

[1] http://www.ti.com/lit/ds/symlink/pcf8575.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
2016-08-08 13:32:53 -04:00
Chen-Yu Tsai
4694dc56e9 sunxi: gpio: Add .xlate function for gpio phandle resolution
sunxi uses a 2 cell phandle for gpio bindings. Also there are no
seperate nodes for each pin bank.

Add a custom .xlate function to map gpio phandles to the correct
pin bank device. This fixes gpio_request_by_name usage.

Fixes: 7aa9748584 ("dm: sunxi: Modify the GPIO driver to support driver
		      model")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2016-07-31 21:45:12 +02:00
Masahiro Yamada
4e3d84066e ARM: uniphier: use (devm_)ioremap() instead of map_sysmem()
This does not have much impact on behavior, but makes code look more
more like Linux.  The use of devm_ioremap() often helps to delete
.remove callbacks entirely.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-24 00:13:10 +09:00
Hamish Martin
4b689f02ff dm: gpio: MPC85XX GPIO platform data support
Define a platform data structure for the MPC85XX GPIO driver to allow
use of the driver without device tree. Users should define the GPIO
blocks for their platform like this:
  struct mpc85xx_gpio_plat gpio_blocks[] = {
         {
                 .addr = 0x130000,
                 .ngpios = 32,
         },
         {
                 .addr = 0x131000,
                 .ngpios = 32,
         },
  };

  U_BOOT_DEVICES(my_platform_gpios) = {
         { "gpio_mpc85xx", &gpio_blocks[0] },
         { "gpio_mpc85xx", &gpio_blocks[1] },
  };

This is intended to build upon the recent submission of the base
MPC85XX driver from Mario Six. We need to use that new driver
without dts support and this patch gives us that flexibility.
This has been tested on a Freescale T2080 CPU, although only the first
GPIO block.

Signed-off-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Reviewed-by: Mario Six <mario.six@gdsys.cc>
Tested-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Simon Glass <sjg@chromium.org>
2016-07-11 14:06:44 -06:00
mario.six@gdsys.cc
fc76b69873 gpio: pca953x: Fix register reading past 8th GPIO
A bug in the pca953x driver prevents correct reading of GPIO input
values beyond the 8th GPIO; all values are reported as zero. Setting of
GPIO output values is not affected.

This patch fixes the reading behavior.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Peng Fan <van.freenix@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-06-19 17:05:55 -06:00
Tom Rini
fd9102dafe Merge branch 'master' of git://git.denx.de/u-boot-atmel 2016-06-13 08:50:58 -04:00
Marek Vasut
152ac5fabf gpio: at91: Fix pullup/pulldown configuration on PIO3
On systems with PIO3 (SAMA5D3/D4/..), the pullup and pulldown configuration
is mutualy exclusive. This patch assures that the opposite pull resistor gets
disabled before the requested pull resistor is enabled. This changes behavior
of at91_set_pio_pulldown() such that the pullup is only disabled if pulldown
is to be enabled. This changes behavior of at91_set_pio_pullup() such that
the pulldown is only disabled if pullup is to be enabled.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Josh Wu <josh.wu@atmel.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-06-12 23:49:38 +02:00
Bin Meng
9769e05bcf x86: broadwell: gpio: Remove the codes to set up pin control
Now that we have set up pin control in cpu_init_r(), remove the
duplicated codes in the broadwell gpio driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-12 12:19:35 +08:00
Bin Meng
d8906c1f3f x86: Probe pinctrl driver in cpu_init_r()
At present pinctrl driver gets probed in ich6_gpio driver's probe
routine, which has two issues:

 - Pin's PADs only gets configured when GPIO driver is probed, which
   is not done by default. This leaves the board in a partially
   functional state as we must initialize PADs correctly to get
   perepherals fully working.
 - The probe routine of pinctrl driver is called multiple times, as
   normally there are multiple GPIO controllers. It should really
   be called just once.

Move the call to syscon_get_by_driver_data() from ich6_gpio driver
to cpu_init_r().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: George McCollister <george.mccollister@gmail.com>
Tested-by: George McCollister <george.mccollister@gmail.com>
2016-06-12 12:19:35 +08:00
Bin Meng
8142340ee3 x86: ich6_gpio: Output return value of syscon_get_by_driver_data()
The call to syscon_get_by_driver_data() does not save its return value.
Print it out to aid debugging.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-12 12:19:35 +08:00
Tom Rini
cc749523ae Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2016-06-04 12:12:26 -04:00
mario.six@gdsys.cc
743268f514 dm: test: Add GPIO open drain tests
Add some tests for the new open drain setting feature of the GPIO
uclass, and extend the capabilities of the sandbox GPIO driver
accordingly.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 22:14:20 -07:00
mario.six@gdsys.cc
51781783c5 dm: gpio: Implement open drain for MPC85XX GPIO
This patch implements the open-drain setting feature for the MPC85XX
GPIO controller.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 22:14:12 -07:00
mario.six@gdsys.cc
53ecdfb920 dm: gpio: Add methods for open drain setting
Certain GPIO devices have the capability to switch their GPIOs into
open-drain mode, that is, instead of actively driving the output
(Push-pull output), the pin is connected to the collector (for a NPN
transistor) or the drain (for a MOSFET) of a transistor, respectively.
The pin then either forms an open circuit or a connection to ground,
depending on the state of the transistor.

This patch adds functions to the GPIO uclass to switch GPIOs to
open-drain mode on devices that support it.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 22:13:52 -07:00
mario.six@gdsys.cc
07d31f8f98 dm: gpio: Add driver for MPC85XX GPIO controller
This patch adds a driver for the built-in GPIO controller of the MPC85XX
SoC (probably supporting other PowerQUICC III SoCs as well).

Each GPIO bank is identified by its own entry in the device tree, i.e.

gpio-controller@fc00 {
      #gpio-cells = <2>;
      compatible = "fsl,pq3-gpio";
      reg = <0xfc00 0x100>
}

By default, each bank is assumed to have 32 GPIOs, but the ngpios
setting is honored, so the number of GPIOs for each bank in configurable
to match the actual GPIO count of the SoC (e.g. the 32/32/23 banks of
the P1022 SoC).

The usual functions of GPIO drivers (setting input/output mode and output
value setting) are supported.

The driver has been tested on MPC85XX, but it is likely that other
PowerQUICC III devices will work as well.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-03 22:13:24 -07:00
Tom Rini
f15715afea Merge branch 'master' of git://git.denx.de/u-boot-tegra 2016-06-03 16:30:47 -04:00
Marek Vasut
307c0b5189 gpio: mxs: Remove netdev.h
The MXS certainly does not support any sort of networking in GPIO code,
remove the netdev.h header.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-02 21:21:41 -04:00
Stephen Warren
074a1fdd27 gpio: add Tegra186 GPIO driver
Tegra186's GPIO controller register layout is significantly different from
previous chips, so add a new driver for it. In fact, there are two
different GPIO controllers in Tegra186 that share a similar register
layout, but very different port mapping. This driver covers both.

The DT binding is already present in the Linux kernel (in linux-next via
the Tegra tree so far).

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org> # v1
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-05-31 09:54:24 -07:00
Stephen Warren
601800be22 ARM: tegra: convert CONFIG_TEGRA_GPIO to Kconfig
Future chips will contain different GPIO HW. This change will enable
future SoC support to select the appropriate GPIO driver for their HW,
in a future-looking fashion, using Kconfig.

TEGRA_GPIO is not simply selected by TEGRA_COMMON (even though all
current Tegra chips used this GPIO HW) to simplify the later addition
of support for Tegra SoCs that use different GPIO HW.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-05-31 09:53:57 -07:00
Tom Rini
e4a94ce4ac Merge git://git.denx.de/u-boot-dm
For odroid-c2 (arch-meson) for now disable designware eth as meson
now needs to do some harder GPIO work.

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	lib/efi_loader/efi_disk.c

Modified:
	configs/odroid-c2_defconfig
2016-05-27 20:34:12 -04:00
mario.six@gdsys.cc
71db3270db dm: gpio: pca953x: Support PCA953X with 40 GPIOs
A DM driver for PCA953x was recently introduced by Peng Fan, which lacked
support for the 40 GPIO versions.

This patch adds support for these chips.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Peng Fan  <van.freenix@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-05-27 09:56:20 -04:00