Commit Graph

14547 Commits

Author SHA1 Message Date
Joe Hershberger
72ff004258 test: eth: Add a test for the target being pinged
The target will respond to pings while doing other network handling.
Make sure that the response happens and is correct.

This currently corrupts the ongoing operation of the device if it
happens to be awaiting an ARP reply of its own to whatever serverip it
is attempting to communicate with. In the test, add an expectation that
the user operation (ping, in this case) will fail. A later patch will
address this problem.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:29:00 -05:00
Joe Hershberger
45988dae4c test: eth: Add a test for ARP requests
This tests that ARP requests made to this target's IP address are
responded-to by the target when it is doing other networking operations.

This currently corrupts the ongoing operation of the device if it
happens to be awaiting an ARP reply of its own to whatever serverip it
is attempting to communicate with. In the test, add an expectation that
the user operation (ping, in this case) will fail. A later patch will
address this problem.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:29:00 -05:00
Joe Hershberger
9cbe5972c3 net: sandbox: Add a priv ptr for tests to use
Tests need to be able to pass their "unit test state" to the handlers
where asserts are evaluated. Add a function that allows the tests to set
this private data on the sandbox eth device.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:59 -05:00
Joe Hershberger
c67a420781 net: sandbox: Allow fake eth to handle more than 1 packet response
Use up to the max allocated receive buffers so as to be able to test
more complex situations.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:58 -05:00
Joe Hershberger
76a503439e net: sandbox: Share the priv structure with tests
If tests want to implement tx handlers, they will likely need access to
the details in the priv structure.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:57 -05:00
Joe Hershberger
c7eb733d60 net: sandbox: Make the fake eth driver response configurable
Make the send handler registerable so tests can check for different
things.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:57 -05:00
Joe Hershberger
e95bb16110 net: sandbox: Refactor sandbox send function
Make the behavior of the send function reusable.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2018-10-10 12:28:56 -05:00
Jens Wiklander
0a60a81ba3 Kconfig: sandbox: enable cmd_avb and dependencies
Enables cmd_avb and its dependencies need to run the AVB tests.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
[trini: Disable for sandbox_noblk]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-07 13:34:19 -04:00
Jens Wiklander
fe39e8e0ee sandbox: imply CONFIG_TEE (TEE uclass)
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-10-07 10:48:26 -04:00
Jens Wiklander
fa830ae1e4 sandbox: dt: add sandbox_tee node
Adds a sandbox_tee node to enable the sandbox tee driver in all the
sandbox dts files.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-10-07 10:48:26 -04:00
Jens Wiklander
7ab5630a42 arm: dt: hikey: Add optee node
Sync with 14e21cb8f811 ("arm64: dt: hikey: Add optee node"
from Linux kernel.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2018-10-07 10:47:38 -04:00
Patrice Chotard
362612df53 mach-stm32: Set MPU SDRAM size to 512MB for STM32F7/H7
This allows to boot all STM32F7 and STM32H7 boards independently
of the amount of embedded SDRAM.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
2018-10-06 14:09:41 -04:00
Adam Ford
5ad4212ce0 ARM: DTS: Add Logic PD OMAP35/DM37 SOM-LV and OMAP35 Torpedo
With the device trees doing most of the work of pin-muxing and
DM doing much of the peripheral initialization, this creates
new defconfig files for each of the Logic PD variants with
proper register settings/pin-muxing.

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Update MAINTAINERS entry]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-06 14:09:27 -04:00
Adam Ford
e2e30f50a9 ARM: DTS: Add support for Logic PD OMAP35 Torpedo & SOM-LV
The baseboards and SOM's are virtually identical to their DM37
counterparts, but OMAP36/37 and OMAP3 have some minor register
differences.  With the boards being mostly driven by device trees
now, this synchronizes their respective device trees with linux-omap
for-next branch destined for 4.20 (or whatever the version after 4.19
will be called)

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-10-06 09:04:18 -04:00
Adam Ford
c981cb8dda ARM: DTS: Remove unnecessary u-boot.dtsi options from omap3/36xx
With the introduction of the omap serial driver, the need for some
of these U-Boot specific modifications is gone.  This cleans up
this unnneeded stuff.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-10-06 09:04:18 -04:00
Adam Ford
87555d1415 ARM: DTS: LogicPD-SOM-LV & Torpedo: Resync DTS with Kernel
The device tree entries are from linux-omap's for-next branch
destined to me put into 4.20 (or whatever the version is after 4.19)

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-10-06 09:04:18 -04:00
Tom Rini
14573fb78f Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-10-05 21:17:35 -04:00
Tom Rini
1b484736ce Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2018-10-05 21:17:21 -04:00
Tom Rini
a4b38fca7e Rockchip-focused changes for v2018.11-rc2:
- fixes to rkimage for SPL boot via USB
  - fixes to make_fit_atf.py, incl. entry-point calculation and python3
    compatibility
  - OP-TEE support for ARMv7-based SoCs
  - fixes to RGMII/GMII selection on the RK3328
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Merge tag 'rockchip-for-v2018.11-rc2' of git://git.denx.de/u-boot-rockchip

Rockchip-focused changes for v2018.11-rc2:
 - fixes to rkimage for SPL boot via USB
 - fixes to make_fit_atf.py, incl. entry-point calculation and python3
   compatibility
 - OP-TEE support for ARMv7-based SoCs
 - fixes to RGMII/GMII selection on the RK3328

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-10-05 13:40:42 -04:00
Alexey Brodkin
5396e8b1dd arc: Add support for IoT development kit
The DesignWare ARC IoT Development Kit is a versatile platform
that includes the necessary hardware and software to accelerate
software development and debugging of sensor fusion,
voice recognition and face detection designs.

More information is avaialble here [1] and here [2].

The board is based on real silicon with
ARC EM9D-based Data Fusion IP Subsystem.

It sports a rich set of I/O including
 * DW USB OTG
 * DW MobileStorage (used for micro SD-card)
 * GPIO
 * multiple serial interface including DW APB UART
 * ADC, PWM and eFlash, SRAM and SPI Flash memory
 * Real-Time Clock (RTC)
 * Bluetooth module with worldwide regulatory compliance
   (FCC, IC, CE, ETSI, TELEC)
 * On-board 9-axis sensor (gyro, accelerometer and compass)

Extensible with Arduino, Pmod, mikroBUS connectors and a 2x18
extension header.

One of the most interesting features for developers is built-in
Digilent USB JTAG probe so only micro-USB cable is needed!

[1] https://www.synopsys.com/dw/ipdir.php?ds=arc_iot_development_kit
[2] https://www.synopsys.com/dw/doc.php/ds/cc/iot_dev_kit.pdf

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-05 16:57:00 +03:00
Alexey Brodkin
7fe46b969d ARC: Implement print_cpuinfo()
Once we enable DISPLAY_CPUINFO for ARC we'll see
ARC core family and version printed on boot.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-05 16:55:42 +03:00
Alexey Brodkin
c3dcd508b6 ARC: Add model property to boards .dts
1. This way we sync with Linux kernel where we have model
   set for all ARC boards for quite some time, see [1]

2. Once we enable DISPLAY_BOARDINFO for ARC this info will
   be printed on boot givin some extra data-point about the board

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=618a9cd06dd471ac232f5b27325b24d26eba5571

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-05 16:55:42 +03:00
Alexey Brodkin
56ddae7d91 ARC: Don't pre-define CROSS_COMPILE
Even though arc-linux- prefix is used in ARC prebuilt tools and
in Buildroot there're other options like Linux distro cross-tools
etc where prefix is different so let's not rely on this default.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-10-05 16:55:42 +03:00
Mian Yousaf Kaukab
7009eae890 rockchip: make_fit_atf: make python3 compatible
Make script python3 compatible. No functional changes intended.

Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04 21:15:46 +02:00
Mian Yousaf Kaukab
e4011e8daa rockchip: make_fit_atf: use elf entry point
make_fit_atf.py uses physical address of first segment as the
entry point to bl31. It is incorrect and causes following abort
when bl31_entry() is called:

U-Boot SPL board initTrying to boot from MMC1
"Synchronous Abort" handler, esr 0x02000000
elr: 0000000000000000 lr : 00000000ff8c7e8c
x 0: 00000000ff8e0000 x 1: 0000000000000000
x 2: 0000000000000000 x 3: 00000000ff8e0180
x 4: 0000000000000000 x 5: 0000000000000000
x 6: 0000000000000030 x 7: 00000000ff8e0188
x 8: 00000000000001e0 x 9: 0000000000000000
x10: 000000000007fcdc x11: 00000000002881b8
x12: 00000000000001a2 x13: 0000000000000198
x14: 000000000007fdcc x15: 00000000002881b8
x16: 00000000003c0724 x17: 00000000003c0718
x18: 000000000007fe80 x19: 00000000ff8e0000
x20: 0000000000200000 x21: 00000000ff8e0000
x22: 0000000000000000 x23: 000000000007fe30
x24: 00000000ff8d1c3c x25: 00000000ff8d5000
x26: 00000000deadbeef x27: 00000000000004a0
x28: 000000000000009c x29: 000000000007fd90

Fix it by using the entry point from the elf header.

Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@suse.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04 21:15:46 +02:00
Kever Yang
aabb51da59 rockchip: add fit source file for pack itb with op-tee
We package U-Boot and OP-TEE into one itb file for SPL,
so that we can support OP-TEE in SPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04 21:15:46 +02:00
Kever Yang
f00273a3a3 rockchip: make_fit_atf: fix warning unit_address_vs_reg
Patch fix warning:
/builddir/BUILD/u-boot-2018.05-rc2/"arch/arm/mach-rockchip/make_fit_atf.py" \
arch/arm/dts/rk3399-firefly.dtb > u-boot.its
  ./tools/mkimage  -f u-boot.its -E u-boot.itb >/dev/null  && cat
/dev/null
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/uboot@1
has a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@1 has
a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@2 has
a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/atf@3 has
a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node /images/fdt@1 has
a unit name, but no reg property
u-boot.itb.tmp: Warning (unit_address_vs_reg): Node
/configurations/config@1 has a unit name, but no reg property
make[1]: Leaving directory
'/builddir/BUILD/u-boot-2018.05-rc2/builds/firefly-rk3399'

Reported-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2018-10-04 21:15:46 +02:00
Tom Rini
a1588ac822 Rockchip changes for 2018.11
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Merge tag 'rockchip-for-v2018.11' of git://git.denx.de/u-boot-rockchip

Rockchip changes for 2018.11
2018-10-03 12:09:19 -04:00
Ooi, Joyce
8be11fb3c1 arm: socfpga: stratix10: add sgmii in phymode setup
Additional sgmii phymode is added in socfpga_phymode_setup() along with
a minor fix for maximum number of GMACs.

Signed-off-by: Ooi, Joyce <joyce.ooi@intel.com>
2018-10-03 12:56:50 +02:00
Ley Foon Tan
74c78024a0 arm: socfpga: Remove unused function socfpga_emac_manage_reset()
Remove code from the reset manager that is never called.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2018-10-03 12:56:50 +02:00
Marek Vasut
806df252c1 ARM: rmobile: Enable PHY framework on Gen3
Enable PHY framework on Gen3, this is required for USB EHCI PHY support.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03 12:56:13 +02:00
Marek Vasut
c1ec347638 ARM: rmobile: Mark 4-64GiB as DRAM on Gen3
Mark area 0x1_0000_0000 - 0x10_0000_0000 as DRAM on Gen3 as the
chip is capable of addressing that and U-Boot can make use of it.
This patch prevents exception when accessing those areas.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03 12:56:13 +02:00
Marek Vasut
2da6d39e26 ARM: dts: rmobile: Reinstate missing i2c6 on Porter
The I2C6 is used to communicate with the PMIC and it was removed
during DT sync with Linux 4.17. Reinstate it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-10-03 12:56:12 +02:00
Heinrich Schuchardt
5845f66123 riscv: allow native compilation
If environment variable CROSS_COMPILE is not set, this indicates native
compilation. In this case we should not set an arbitrary value which is
not applicable for 64bit anyway.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-10-03 17:49:44 +08:00
Rick Chen
9d9b3dc0d5 riscv: cosmetic: Reword do_reset() printf message.
The Sentence "reset unsupported yet" is not
grammatically correct and should say
"reset not supported yet" instead.

Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Signed-off-by: Rick Chen <rick@andestech.com>
2018-10-03 17:49:27 +08:00
Bin Meng
b984ddc2dd riscv: Move do_reset() to a common place
We don't have a reset method on any RISC-V board yet. Instead of
adding the same 'unsupported' message for each CPU variant it might
make more sense to add a generic do_reset function for all CPU
variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c).

Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:43 +08:00
Bin Meng
510e379c49 riscv: Add QEMU virt board support
This adds QEMU RISC-V 'virt' board target support, with the hope of
helping people easily test U-Boot on RISC-V.

The QEMU virt machine models a generic RISC-V virtual machine with
support for the VirtIO standard networking and block storage devices.
It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and
it also uses device-tree to pass configuration information to guest
software. It implements RISC-V privileged architecture spec v1.10.

Both 32-bit and 64-bit builds are supported. Support is pretty much
preliminary, only booting to U-Boot shell with the UART driver on
a single core. Booting Linux is not supported yet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:37 +08:00
Bin Meng
cd1f45c21d riscv: kconfig: Imply DM support for some common drivers
This implies DM support for some common drivers that are used on
RISC-V.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:31 +08:00
Bin Meng
bf6cc82c7c riscv: kconfig: Select DM and OF_CONTROL
RISC-V is a pretty new architecture and should support DM and
OF_CONTROL by default.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:25 +08:00
Bin Meng
4694c93fef riscv: ae350: Clean up mixed tabs and spaces in the dts
There are quite a lot of mixed tabs and spaces in the ae350.dts.
Clean them up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:19 +08:00
Bin Meng
b5369c5813 riscv: Make start.S available for all targets
Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
common for all RISC-V targets.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:48:14 +08:00
Bin Meng
ed49ba4dcc riscv: bootm: Pass mhartid CSR value to kernel
So far this is hardcoded to zero, and we should read the value from
mhartid CSR and pass it to Linux kernel.

Suggested-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-10-03 17:48:08 +08:00
Bin Meng
e5ea1e5860 riscv: Remove CSR read/write defines in encoding.h
There is no reason to keep two versions of CSR read/write defines
in encoding.h. We already have one set of defines in csr.h, which
is from Linux kernel, and let's drop the one in encoding.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-10-03 17:48:02 +08:00
Bin Meng
2fab2e9c88 riscv: Add a helper routine to print CPU information
This adds a helper routine to print CPU information. Currently
it prints all the instruction set extensions that the processor
core supports.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:47:55 +08:00
Bin Meng
ce7a8e0740 riscv: Explicitly pass -march and -mabi to the compiler
At present the compiler flag against which architecture and abi
variant the riscv image is built for is not explicitly indicated
which means the default compiler configuration is used. But this
does not work if we want to build a different target (eg: 32-bit
riscv images using a toolchain configured for 64-bit riscv).

Fix this by explicitly passing -march and -mabi to the compiler.
Since generically we don't use floating point in U-Boot, specify
the RV[32|64]IMA ISA and software floating ABI.

This also fix some alignment coding style issues.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:47:43 +08:00
Bin Meng
3d6015651b riscv: Fix coding style issues in the linker script
There are several coding style issues in the linker script. Fix them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:47:37 +08:00
Bin Meng
dfb828ed1c riscv: Move the linker script to the CPU root directory
The linker script can be shared by all RISC-V targets. Move it to
a common place.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:47:31 +08:00
Bin Meng
8cdc6b58d7 riscv: Remove mach type
Since the mach_id is not used by RISC-V, remove it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:47:19 +08:00
Bin Meng
4afeedf172 riscv: bootm: Correct the 1st kernel argument to hart id
The first argument of Linux kernel is the risc-v core hart id,
from which the kernel is booted from. It is not the mach_id,
which seems to be copied from arm.

While we are here, this also changes the Linux kernel entry
parameters' type to support both 32-bit and 64-bit.

Note the hart id is hardcoded to zero for now, and we should
change to fill in it with the value read from mhartid CSR of
the hart which this routine is currently running on.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
2018-10-03 17:46:51 +08:00
Bin Meng
3ad4866dd7 riscv: Remove setup.h
This was copied from ARM, and does not apply to RISC-V. While we
are here, bootm.h is eventually removed as its content is only
the inclusion of setup.h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2018-10-03 17:44:44 +08:00