Commit Graph

72310 Commits

Author SHA1 Message Date
Giulio Benetti
45dae4a3c7 board: freescale: imxrt1020-evk: fix console is not enabled while init dram
While initializing dram in spl_dram_init(), mdelay() is called that in
order calls get_ticks() that  verifies if timer exists, if doesn't, it
throws a panic(), but since preloader_console_init() has still not been
called those panic()s will fail. This doesn't help debugging, so let's
setup console before calling spl_dram_init() by moving it after
spl_dram_init().

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
2021-04-08 20:29:53 +02:00
Adam Ford
8166bb2428 configs: imx8mn_beacon: Enable QSPI Support
There is a QSPI chip connected to the FSPI.  Enable the defconfig
to support it.

Signed-off-by: Adam Ford <aford173@gmail.com>
2021-04-08 20:29:53 +02:00
Adam Ford
a5f8cc3301 arm: dts: imx8mn, imx8mn-beacon: Sync dts files with Kernel 5.12-rc5
There have been a few updates including flexspi, so it's necessary
to re-sync.

Signed-off-by: Adam Ford <aford173@gmail.com>
2021-04-08 20:29:53 +02:00
Peter Robinson
f980299004 ARM: board: usbarmory: Convert to OF_CONTROL and DM
Convert usbarmory to OF_CONTROL and DM for gpio, pin
usb support on the i.MX53 based usbarmory.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Cc: Andrej Rosano <andrej@inversepath.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2021-04-08 20:29:53 +02:00
Peter Robinson
bfa0d04e86 ARM: board: usbarmory: Import the usbarmory dts file
Import the iMX53 based usbarmory dts files from Linux 5.12-rc1

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Cc: Andrej Rosano <andrej@inversepath.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-04-08 20:29:53 +02:00
Oleksandr Suvorov
f5c2c3705b board: toradex: apalis-imx8x: fix build instructions
Fix an URL for downloading the SCFW binary for an Apalis iMX8X
and improve u-boot image build instructions.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-04-08 20:29:53 +02:00
Oleksandr Suvorov
54398740ca apalis/colibri_imx6: remove video= settings
Since Toradex provides the full set of overlays for Linux kernel
for display interfaces for both Apalis iMX6Q and Colibri iMX6DL
modules, the video= settings are obsolete. Remove them.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-04-08 20:29:53 +02:00
Philippe Schenker
fdbf0e51ff colibri_imx6ull/imx7: add missing tdxargs variable
All the other boards have tdxargs specified for setting manual kernel
command-line arguments. Add them also to NAND-based boards.

Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-04-08 20:29:53 +02:00
Igor Opaniuk
3470b45aba colibri_imx6: adjust boot order
Remove duplicate of mmc0, set this boot order:
1) SD
2) eMMC
3) USB
4) DHCP boot

Fixes: 0e15165bc4 ("colibri_imx6: boot env configuration updates")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-04-08 20:29:53 +02:00
Tim Harvey
72b3732d24 board: gateworks: venice: increase CONFIG_SYS_SPL_MALLOC_SIZE
commit 03f1f78a9b ("spl: fit: Prefer a malloc()'d buffer for loading images")'
changed the way buffer allocation worked for SPL to a more flexible
method.

For venice this caused breakage that is resolved by increasing the size
of CONFIG_SYS_SPL_MALLOC_SIZE as the current FIT slighly exceeds 512KiB.

Additionally remove the unnecessary comment on CONFIG_SPL_BSS_MAX_SIZE
and CONFIG_SYS_SPL_MALLOC_SIZE as the size is obvious from the define.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-04-08 20:29:53 +02:00
Tim Harvey
bb32c2a617 board: gateworks: venice: fix gsc_get_dev
use dm_i2c_probe instead of i2c_get_chip which appears to be more
reliable.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-04-08 20:29:53 +02:00
Fabio Estevam
aeee33d6e0 MAINTAINERS: Use my personal e-mail address
Use my personal e-mail address for U-Boot related work.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2021-04-08 20:29:53 +02:00
Tim Harvey
ca3ac1e32a imx: ventana: enable dm for SPI
Enable driver model for SPI which allows us to remove the iomux
and init.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-04-08 20:29:53 +02:00
Tim Harvey
777f333c37 imx: ventana: enable dm for MTD and NAND
Enable driver model for MTD and NAND support allowing us to remove
the iomux, init, and most of the static configuration.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-04-08 20:29:53 +02:00
Tim Harvey
19a387f85d imx: ventana: enable dm support for MMC and SATA
Enable driver model support for MMC and SATA.

Note that DM_MMC requires aliases for your mmc devices so
they are added to the dts. Linux does not support enumerating mmc
devices by alias so these are not present in the Linux dts.

Note that we still need board_mmc_init() and board_mmc_getcd() for
not DM SPL to support MMC.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-04-08 20:29:53 +02:00
Tim Harvey
72c46327f0 imx: ventana: enable dm support for USB
Enable dm support for USB (which also requires dm support for fixed
regulators used for vbus enable) and remove usb iomux which is no
longer needed.

We can remove the handling of otgpwr_en gpio as this is defined in
dt as usbotg vbus-supply but we need to keep the handling of
USB_HUB_RST# for boards that have a USB HUB as that isn't defined in
the dt's currently.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-04-08 20:29:53 +02:00
Tim Harvey
ee025c13b2 imx: ventana: add pinctrl and remove unneeded UART init and config
Once the IMX6 pinctrl driver is added UART is fully using driver mode
so we no longer need to config and initialize it.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-04-08 20:29:53 +02:00
Tim Harvey
d863d05439 imx: ventana: convert U-Boot to OF_CONTROL using FIT image
In preparation for dm conversion convert to OF_CONTROL by adding FIT image
support and multi dtb.

Add a board_fit_config_name_match to match the dtb based off of EEPROM
model.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-04-08 20:29:53 +02:00
Tim Harvey
13acc63e84 arm: dts: imx6qdl-gw*: add dr_mode prop to dt to avoid error
The fsl-usb dt bindings in Linux default dr_mode to 'host' for
backward compatibility however U-Boot prints an error if
this property does not exist. Declare it in the Gateworks
Ventana device-trees to avoid the error.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-04-08 20:29:53 +02:00
Tim Harvey
acb9a13b50 imx: ventana: add Gateworks Ventana dts
Add Gateworks Ventana dts/dtsi files from Linux 5.11 in preparation for
conversion to driver-model.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-04-08 20:29:53 +02:00
Tim Harvey
d331cee596 dt-bindings: add tda1997x and bindings
Add td1997x header from Linux to be included by dts files.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-04-08 20:29:53 +02:00
Tim Harvey
aa0032f672 spl: fit: nand: allow for non-page-aligned elements
Add a weak nand_get_mtd function for nand drivers to provide mtd info
and use this to set pagesize such that reading of non page-aligned
elements can succeed.

The spl_load_simple_fit already handles block block access so all we
need to do is provide the nand writesize as the block length.

Further cleanup of the drivers which use nand_spl_loaders.c such as
am335x_spl_bch.c, atmel_nand.c, and nand_spl_simple.c could be done
using info from mtd_info instead of statically defined details.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-04-08 20:29:53 +02:00
Tim Harvey
39cb85043c spl: fit: nand: skip bad block handling if NAND chip not fully defined
commit 9f6a14c47f ("spl: fit: nand: fix fit loading in case of bad blocks")
added support for adjusting the image offset to account for bad blocks.
However this requires nand_spl_adjust_offset() which requires fully defined
specifics of the NAND chip being used may not be avialable.

Allow skipping this support for drivers or configs which don't specify
the NAND chip details statically with defines.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-04-08 20:29:53 +02:00
Marek Vasut
09d86eab14 ARM: imx: Add OCRAM_S into iMX8M MMU tables
The OCRAM_S is regular memory, just like the OCRAM, add it to the MMU
tables so it can be used and cached.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2021-04-08 20:29:53 +02:00
Peng Fan
8a78e31d73 doc: imx8mp-evk: update after using binman
update doc after using binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08 20:29:53 +02:00
Peng Fan
1e4ed2d69d imx8mp-evk: switch to use binman
Use binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08 20:29:53 +02:00
Peng Fan
1ba917e150 doc: imx8mn_evk: update doc after using binman
Update doc after using binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08 20:29:53 +02:00
Peng Fan
d6afc6b3a0 imx8mn-evk: switch to use binman
Use binman to pack images.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08 20:29:53 +02:00
Peng Fan
353dfe4b43 imx8mn-ddr4-evk: switch to use binman
Use binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08 20:29:53 +02:00
Peng Fan
a505fd3cc6 doc: imx8mm_evk: update doc after using binman
Update doc after switch to binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08 20:29:53 +02:00
Peng Fan
8996e6b7c6 imx8mm_evk: switch to use binman to pack images
Use binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08 20:29:53 +02:00
Ye Li
2ff17d2f74 crypto: fsl: refactor for 32 bit version CAAM support on ARM64
Previous patch "MLK-18044-4: crypto: caam: Fix pointer size to 32bit
for i.MX8M" breaks the 64 bits CAAM.

Since i.MX CAAM are all 32 bits no matter the ARM arch (32 or 64),
to adapt and not break 64 bits CAAM support,  add a new config
CONFIG_CAAM_64BIT and new relevant type "caam_dma_addr_t".

This config is default enabled when CONFIG_PHYS_64BIT is set except
for iMX8M.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08 20:29:53 +02:00
Breno Lima
58fc03e2a6 fsl_mfgprot: Fix typo in sign_mppubk()
The signature is generated using manufacturing protection private key.

Fix typo in fsl_mfgprot.c.

Signed-off-by: Breno Lima <breno.lima@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08 20:29:52 +02:00
Clement Faure
69f542ca2b imx8: Add DEK blob encapsulation
Add DEK encapsulation support for imx8. The DEK blob is generated by the
SECO through the SCFW API.

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08 20:29:52 +02:00
Clement Faure
56d2050f40 imx8m: Add DEK blob encapsulation for imx8m
Add DEK blob encapsulation support for IMX8M through "dek_blob" command.
On ARMv8, u-boot runs in non-secure, thus cannot encapsulate a DEK blob
for encrypted boot.
The DEK blob is encapsulated by OP-TEE through a trusted application call.
U-boot sends and receives the DEK and the DEK blob binaries through OP-TEE
dynamic shared memory.

To enable the DEK blob encapsulation, add to the defconfig:
CONFIG_SECURE_BOOT=y
CONFIG_FAT_WRITE=y
CONFIG_CMD_DEKBLOB=y

Signed-off-by: Clement Faure <clement.faure@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08 20:29:52 +02:00
Clement Le Marquis
613cf239ed imx: caam: new u-boot command to set PRIBLOB bitfield from CAAM SCFGR register to 0x3
It is highly recommended to set the PRIBLOB bitfield to 0x3 once your
encrypted boot image has booted up, this prevents the generation of new
blobs that can be used to decrypt an encrypted boot image. The PRIBLOB is
a sticky type bit and cannot be changed until the next power on reset.

Add the set_priblob_bitfield U-Boot command to prevent the generation of
new blobs.

Signed-off-by: Clement Le Marquis <clement.lemarquis@nxp.com>
Acked-by: Ye Li <Ye.Li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2021-04-08 20:29:52 +02:00
Tom Rini
f6127db8cc Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
- Watchdog, Unleashed and Icicle improvements
2021-04-08 07:33:14 -04:00
Tom Rini
8246654e1e Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Add Armada 38x RTC driver (Marek)
- turris_omnia: Misc updates (enable RTC and other cmds) (Marek)
- ds414: Misc updates (enable XHCI_PCI USB support etc) (Phil)
- Convert MVEBU MMC driver to DM (Harm)
- kirkwood: Misc updates and cleanups to some boards (Harm)
2021-04-08 07:32:54 -04:00
Siew Chin Lim
96fe4f6485 arm: socfpga: smc: Add function to get usercode
Add function to send mailbox command via SMC to get usercode from SDM.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08 17:29:13 +08:00
Siew Chin Lim
cdca986070 arm: socfpga: Enable FIT signature with crc32 for SOC64 devices
Add signature with crc32 value for all images in binman node for FIT
image in device tree. And, enable FIT signature checking for Stratix10
and Agilex ATF and VAB sdmmc boot.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08 17:29:13 +08:00
Siew Chin Lim
404a98b0a4 arm: socfpga: Changed to store QSPI reference clock in kHz
Changed to store QSPI reference clock in kHz instead of Hz in
boot scratch cold0 register for Stratix10 and Agilex.

This patch is in preparation for Intel N5X SDRAM driver
support. Reserved 4 bits for Intel N5X SDRAM driver,
and there will be 28 bits to store QSPI reference clock.
Due to limited bits, QSPI reference clock frequency is
converted to kHz from Hz.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-04-08 17:29:12 +08:00
Siew Chin Lim
3aef59f280 arm: socfpga: Move Stratix10 and Agilex clock manager common code
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08 17:29:12 +08:00
Siew Chin Lim
e2ffb1da1d arm: socfpga: Restructure Stratix10 and Agilex handoff code
Restructure Stratix10 and Agilex handoff code to used by
all SOC64 devices, in preparation to support handoff for
Diamond Mesa.

Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c
which contains the generic function to parse the handoff
data.

Update system_manager_soc64.c to use generic handoff
function in wrap_handoff_soc64.c.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08 17:29:12 +08:00
Siew Chin Lim
a73514a8d2 arm: socfpga: Rearrange sequence of macros in handoff_soc64.h
Rearrange sequence of macros in handoff_soc64.h without any functionality
change. In preparation for Stratix10 and Agilex handoff function
restructuring.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08 17:29:12 +08:00
Siew Chin Lim
bab26535cc arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c
Rename to common file name to used by all SOC64 devices.
No functionality change.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08 17:29:12 +08:00
Siew Chin Lim
d623e52c9f arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c
Rename to common file name to used by all SOC64 devices.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08 17:29:12 +08:00
Siew Chin Lim
8f337f3721 arm: socfpga: Rename Stratix10 and Agilex handoff common macros
Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from
S10_HANDOFF to SOC64_HANDOFF.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-04-08 17:29:12 +08:00
Siew Chin Lim
f86ed75059 arm: socfpga: Move Stratix10 and Agilex SPL common code
Move Stratix10 and Agilex SPL common code to spl_soc64.c.
We are in preparation for new n5x device support.
No functional change in this patch.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08 17:29:11 +08:00
Siew Chin Lim
4e521e1430 arm: socfpga: smc: Remove unused SMC function ID
Remove unused SMC function ID 61 and 62.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2021-04-08 17:29:11 +08:00
Bin Meng
e7bb113cc4 riscv: dts: mpfs-icicle-kit: Drop 'clock-frequency' in the uart nodes
The uart nodes already provide <clocks> property for the driver to
dynamically calculate the correct clock frequency. There is no need
to keep the hard-coded <clock-frequency> property.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
2021-04-08 15:37:30 +08:00