2 Commits

Author	SHA1	Message	Date
Michal Simek	01a6da1661	xilinx: Fix xlnx,mio_bank property ... s/xlnx,mio_bank/xlnx,mio-bank/g DT binding is describing mio-bank not mio_bank that's why fix all DTSes and also driver itself. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Peng Fan <peng.fan@nxp.com>	2020-08-20 09:49:20 +02:00
Luca Ceresoli	ac80ac09c8	arm64: zynqmp: add support for Avnet UltraZed-EV Starter Kit ... Avnet UltraZed-EV Starter Kit is composed by the UltraZed-EV SoM and the only publicly-available compatible carrier card. The SoM is based on the EV version of the Xilinx ZynqMP SoC+FPGA. The psu_init_gpl.c file has been generated from the board definition files at [0] using Vivado 2018.3 and then minimized by tools/zynqmp_psu_init_minimize.sh. Manually removed serdes init code since it is not mentioned in device tree and fixed a checkpatch error. [0] 3686c9ff7d/ultrazed_7ev_cc/1.1 Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>	2019-07-30 10:20:06 +02:00