Android Boot Image v2 adds "DTB" payload (and corresponding field in the
image header). Provide functions for its handling:
- android_image_get_dtb_by_index(): Obtain DTB blob from "DTB" part of
boot image, by blob's index
- android_image_print_dtb_contents(): Iterate over all DTB blobs in
"DTB" part of boot image and print those blobs info
"DTB" payload might be in one of the following formats:
1. concatenated DTB blobs
2. Android DTBO format
The latter requires "android-image-dt.c" functionality, so this commit
selects that file for building for CONFIG_ANDROID_BOOT_IMAGE option.
Right now this new functionality isn't used, but it can be used further.
As it's required to apply some specific dtbo blob(s) from "dtbo"
partition, we can't automate this process inside of "bootm" command. But
we can do next:
- come up with some new command like "abootimg" to extract dtb blob
from boot image (using functions from this patch)
- extract desired dtbo blobs from "dtbo" partition using "adtimg"
command
- merge dtbo blobs into dtb blob using "fdt apply" command
- pass resulting dtb blob into bootm command in order to boot the
Android kernel with Android ramdisk from boot image
Signed-off-by: Sam Protsenko <joe.skb7@gmail.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The code in this file is not specific to Apollo Lake. According to
coreboot sources (where this code comes from), it is common to at least:
* Apollo Lake
* Cannon Lake
* Ice Lake
* Skylake
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
ITSS stands for "Interrupt Timer Subsystem", so add that term to the
description of the relevant files.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When ich_spi_exec_op_hwseq() is called to erase a 4k block
(opcode = SPINOR_OP_BE_4K), it expects to find a length value in
op->data.nbytes, but that value is always 0. As a result, the while loop
is never executed and no erase is carried out.
Fix this by dropping the loop code entirely, only keeping the relevant
parts of the loop body.
See http://patchwork.ozlabs.org/patch/1222779/ for more detailed
background information and discussion.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
SFI is quite poor and useless resource provider. Moreover it makes hard
to develop and extend functionality in the Linux kernel.
Enable a necessary minimum to use ACPI on Intel Edison.
Linux kernel have been prepared for this change since v5.4, where the last
crucial driver, i.e. for Basin Cove PMIC, has been submitted.
Note, that stock image won't suffer by this change since it doesn't have
ACPI enabled on the kernel level.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Enable command line editing, because it is extremely convenient.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Use valid restructured text to avoid warnings like
WARNING: Title underline too short.
WARNING: Block quote ends without a blank line; unexpected unindent.
when building with `make htmldocs`.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
The fs segment is only used to get the global data pointer.
If it is accessed beyond sizeof(new_gd->arch.gd_addr), it is a bug.
To specify the byte-granule limit size, drop the G bit, so the
flag field is 0x8093 instead of 0xc093, and set the limit field
to sizeof(new_gd->arch.gd_addr) - 1.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed the comments about FS segement]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
I do not know why the boot code immediately after the system reset
should write-back the cache content. I think the cache invalidation
should be enough.
I tested this commit with qemu-x86_defconfig, and it worked for me.
Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Now, Slim Bootloader uses NS16550_DYNAMIC to support serial port
configuration at runtime, so no more code change is required.
Therefore, remove unnecessary steps and fix minor typo.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Slim Bootloader provides serial port info in its HOB to support
both IO or MMIO serial ports, but it's controlled by SYS_NS16550_MEM32
or SYS_NS16550_PORT_MAPPED in U-Boot.
To support both serial port configurations dynamically at runtime,
Slim Bootloader serial driver leverages NS16550_DYNAMIC.
Signed-off-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: remove the obsolete comments for data->type]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Use this UART to improve the compatibility of U-Boot when used as a
coreboot payload.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Coreboot can provide information about the serial device in use on a
platform. Add a driver that uses this information to produce a working
UART.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Since mid 2016, coreboot has additional fields in the serial struct that
it passes down to U-Boot. Add these so we are in sync.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At present this driver uses an assortment of CONFIG options to control
how it accesses the hardware. This is painful for platforms that are
supposed to be controlled by a device tree or a previous-stage bootloader.
Add a new CONFIG option to enable fully dynamic configuration. This
controls register spacing, size, offset and endianness.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Aiden Park <aiden.park@intel.com>
Tested-by: Aiden Park <aiden.park@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: squashed in http://patchwork.ozlabs.org/patch/1232929/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Migrate CONFIG_DESIGNWARE_WATCHDOG to Kconfig and update the headers
accordingly, no functional change. The S10 enables the WDT only in
SPL, but does not enable it in U-Boot itself, hence disable it in
the config again.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Philipp Tomisch <philipp.tomisch@theobroma-systems.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
This particular chunk of code was not updated, likely due to the order
in which the patches were posted and applied. Fix this missing part.
Fixes: bb25aca134 ("arm: socfpga: Convert reset manager from struct to defines")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
In Cyclone 5 SoC platform, the first USB probing is failed but second
probing is success. DWC2 USB driver read gsnpsid register right after
de-assert reset, but controller is not ready yet and it returns gsnpsid 0.
Polling reset status after de-assert reset to solve the issue.
Retry with this fix more than 10 times without issue.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Add a new option to enable the DROP_FFS flag when flashing UBI images to
NAND in order to drop trailing all-0xff pages.
This is similar to the existing FASTBOOT_FLASH_NAND_TRIMFFS option.
Signed-off-by: Guillermo Rodriguez <guille.rodriguez@gmail.com>
Cc: Lukasz Majewski <lukma@denx.de>
Invalidate dcache line before accessing Setup Packet contents. Otherwise
driver will see stale content on non coherent architecture.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Denali NAND driver changes:
- Set up more registers in denali-spl for SOCFPGA
- Make clocks optional
- Do not assert reset signals in the remove hook
- associate SPARE_AREA_SKIP_BYTES with DT compatible
- switch to UCLASS_MTD
UniPhier platform changes:
- fix a bug in dram_init()
- specify loadaddr for "source" command
-----BEGIN PGP SIGNATURE-----
iQJSBAABCgA8FiEEbmPs18K1szRHjPqEPYsBB53g2wYFAl40VCseHHlhbWFkYS5t
YXNhaGlyb0Bzb2Npb25leHQuY29tAAoJED2LAQed4NsGhyAP/jVioSrrTggWpstI
5dkWwyF5d/p2NdZIwFbEm6tSSmistQIE3Hk7D8vLv6tXRSCIa6Qv3pgQ0mTfRELh
B54yhNs2S7Ur7LyVeHxlVmoIG/6qefd7pGRvgTttXxNkdHi0Ul7wzSBvQJ5v2XCs
dxy8uhEVxzVNHqqnbQq85eZEPB0viiCGe3K/mr6mTGrbnfocbuRgev41/C+54dSb
ssz1VfeSTEmAIlynja4kfUff42yWc6GtFEDoLZQ1CyyOicRpvO1ixL0Jo/k5HptG
thrs3UXplHZbWc7p7Q8JpAv9MyeN+p62ChpqLJSgqB31UmLMhIGk9O799oEkWGTH
Oeqim56I0mC8FkEqEG9xoZ24aGVz7g2TRs4KYA00ZGtjf482zBLLcfoEK7MzKSlj
F61ldTJVOjEd8xNnCPilmVOEuZ1fzCnS8FHaNPDeO437u6GsHs4SnHNdDY3Mnqxj
6pynfYJoXudzN8bnNQ+LQnllOVt7JwFTmlXLaVTeSJeJWIoO6QbOSlCxpLNR+ajb
dc6bFMWScMqElO3UkktxXKbQQOgLKwHUUcgdL4poKksbY3Wq7N3rIfhhVbSLzcyn
Py6mZgVVbMYzYtmirlGj/tzd9LNpb1cH7mVPJsT7eB07co3H7kEdvoCatUEoEaQA
ju63tX0lCg7MEonxWstcIqMGy0Ql
=PvYc
-----END PGP SIGNATURE-----
Merge tag 'uniphier-v2020.04-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier
UniPhier SoC updates for v2020.04 (2nd)
Denali NAND driver changes:
- Set up more registers in denali-spl for SOCFPGA
- Make clocks optional
- Do not assert reset signals in the remove hook
- associate SPARE_AREA_SKIP_BYTES with DT compatible
- switch to UCLASS_MTD
UniPhier platform changes:
- fix a bug in dram_init()
- specify loadaddr for "source" command
If the "source" command is not given the address, it uses
CONFIG_SYS_LOAD_ADDR, which is compile-time determined.
Using the "loadaddr" environment variable is handier because it is
relocated according to the memory base when CONFIG_POSITION_INDEPENDENT
is enabled.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
gd->ram_base is not set at all if the end address of the DRAM ch0
exceeds the 4GB limit.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
UCLASS_MTD is a better fit for NAND drivers.
Make NAND_DENALI_DT depend on DM_MTD, which is needed to compile
drivers/mtd/mtd-uclass.c
Also, make ARCH_UNIPHIER select DM_MTD because all the defconfig
of this platform enables NAND_DENALI_DT.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Now that the reset controlling of the Denali NAND driver (denali_dt.c)
works for this platform, remove the adhoc reset deassert code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently, the denali NAND driver in U-Boot configures the
SPARE_AREA_SKIP_BYTES based on the CONFIG option.
Recently, Linux kernel merged a patch that associates the proper
value for this register with the DT compatible string.
Do likewise in U-Boot too.
The denali_spl.c still uses CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
When the reset signal is de-asserted, the HW-controlled bootstrap
starts running unless it is disabled in the SoC integration.
It issues some commands to detect a NAND chip, and sets up registers
automatically. Until this process finishes, software should avoid
any register access.
Without this delay function, some of UniPhier boards hangs up while
executing nand_scan_ident(). (denali_read_byte() is blocked)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The Denali NAND driver in mainline Linux currently cannot deassert the
reset. The upcoming Linux 5.6 will support the reset controlling, and
also set up SPARE_AREA_SKIP_BYTES correctly. So, the Denali driver in
the future kernel will work without relying on any bootloader or firmware.
However, we still need to take care of stable kernel versions for a while.
U-boot should not assert the reset of this controller.
Fixes: ed784ac382 ("mtd: rawnand: denali: add reset handling")
Signed-off-by: Marek Vasut <marex@denx.de>
[yamada.masahiro: reword the commit description]
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The "nand_x" and "ecc" clocks are currently optional. Make the core
clock optional in the same way. This will allow platforms with no clock
driver support to use this driver.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Marek Vasut <marex@denx.de> # On SoCFPGA Arria V
On Altera SoCFPGA, upon either cold-boot or power-on reset, the
Denali NAND IP is initialized by the BootROM ; upon warm-reset,
the Denali NAND IP is NOT initialized by BootROM. In fact, upon
warm-reset, the SoCFPGA BootROM checks whether the SPL image in
on-chip RAM is valid and if so, completely skips re-loading the
SPL from the boot media.
This does sometimes lead to problems where the software left
the boot media in inconsistent state before warm-reset, and
because the BootROM does not reset the boot media, the boot
media is left in this inconsistent state, often until another
component attempts to access the boot media and fails with an
difficult to debug failure. To mitigate this problem, the SPL
on Altera SoCFPGA always resets all the IPs on the SoC early
on boot.
This results in a couple of register values, pre-programmed by
the BootROM, to be lost during this reset. To restore correct
operation of the IP on SoCFPGA, these values must be programmed
back into the controller by the driver. Note that on other SoCs
which do not use the HW-controlled bootstrap, more registers
may have to be programmed.
This also aligns the SPL behavior with the full Denali NAND
driver, which sets these values in denali_hw_init().
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Since commit e1910d93b8 ("doc: driver-model: Convert MIGRATION.txt to
reST") MIGRATION.txt has been converted to migration.rst, so update
the Makefile references accordingly.
Fixes: e1910d93b8 ("doc: driver-model: Convert MIGRATION.txt to reST")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
In upstream libfdt, 6dcb8ba4 "libfdt: Add helpers for accessing
unaligned words" introduced changes to support unaligned reads for ARM
platforms and 11738cf01f15 "libfdt: Don't use memcpy to handle unaligned
reads on ARM" improved the performance of these helpers.
In practice however, this only occurs when the user has forced the
device tree to be placed in memory in a non-aligned way, which in turn
violates both our rules and the Linux Kernel rules for how things must
reside in memory to function.
This "in practice" part is important as handling these other cases adds
visible (1 second or more) delay to boot in what would be considered the
fast path of the code.
Cc: Patrice CHOTARD <patrice.chotard@st.com>
Cc: Patrick DELAUNAY <patrick.delaunay@st.com>
Link: https://www.spinics.net/lists/devicetree-compiler/msg02972.html
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Patrice Chotard <patrice.chotard@st.com>
Coreutils command nproc can be used on Linux and BSD to count the number of
available CPU cores. Use this instead of relying on the parsing of the
Linux specific proc file system.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
As hinted by GCC 9, there is a return statement that returns
an uninitialized variable in optee_copy_firmware_node().
This patch addresses this.
Signed-off-by: Christoph Müllner <christoph.muellner@theobroma-systems.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
This removes the arch-specific checks for "checkcpu" function from the init
sequence. Make "checkcpu" generic and provide a weak nop stub instead.
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
New analysis by the tool has shown that we have some cases where we
weren't handling the error exit condition correctly. When we ran into
the ENOMEM case we wouldn't exit the function and thus incorrect things
could happen. Rework the unwinding such that we don't need a helper
function now and free what we may have allocated.
Fixes: 18030d04d2 ("GPT: fix memory leaks identified by Coverity")
Reported-by: Coverity (CID: 275475, 275476)
Cc: Alison Chaiken <alison@she-devel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Jordy <jordy@simplyhacker.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This enables readning the cpuid from e-fuse, and deriving a static
MAC address from it.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Add alias for mmc/sdmmc so that we can have a fix mmc number for emmc.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Rockchip use CONFIG_SPL_OPTEE for OPTEE support, which is load and run
before U-Boot, but not use CONFIG_OPTEE which is after U-Boot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Add rk3328-sdram-ddr4-666.dtsi for support ddr4 init.
Signed-off-by: YouMin Chen <cym@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
