The following bard configurations have been without active maintenance
for a long time, and the board maintainer agrees to have them removed:
MPC5200: TOP5200, MINI5200, EVAL5200
MPC860: TOP860
at91sam9xeXXX: top9000eval_xe, top9000su_xe
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
[trini: Add missing Kconfig removals]
Signed-off-by: Tom Rini <trini@ti.com>
The logic of the return statement in sata_port_status() calls for a
bitwise 'AND' operator, not logical 'AND'. Fix the typo.
Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
There is no gaps in exynos gpio enum after rework, so the gpio
numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
There is no gaps in exynos gpio enum after rework, so the gpio
numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
There is no gaps in exynos gpio enum after rework, so the gpio
numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
There is no gaps in exynos gpio enum after rework, so the gpio
numbers should be adjusted to the new numbering.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
The gpy0 don't need any additional register offset,
but the gpx0 does, so now it is fixed.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
The gpf0 offset was bad and it's now fixed.
After fix gpio order in *pinctrl.dts , the gpy0 offset is not required now.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
The pinctrl dts was imported from the kernel, but the order
of GPM and GPY is wrong. The gpio enum in: asm/arch/gpio.h
is proper.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
This config is required by Odroid, and could be also useful for the other
boards.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
The SD Card slot detection pin should be configured as input.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Some boards still use xstr(). Replace remaining occurrences
of xstr() by commonly used __stringify().
Signed-off-by: Anatolij Gustschin <agust@denx.de>
This patch makes the following changes:
- Set kernel entry point correctly
- Append bootargs from image to global bootargs instead
of replacing them
- Return end address instead of size from android_image_get_end()
- Give correct parameter to genimg_get_format() in boot_get_ramdisk()
- Move ramdisk message printing from android_image_get_kernel() to
android_image_get_ramdisk()
Signed-off-by: Ahmad Draidi <ar2000jp@gmail.com>
Cc: Tom Rini <trini@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This file should contain the bin_hdr generated by the original Marvell
U-Boot implementation. As this is currently not included in this
U-Boot version, we have added this placeholder, so that the U-Boot
image can be generated without errors.
If you have a known to be working bin_hdr for your board, then you
just need to replace this text file here with the binary header
and recompile U-Boot.
In a few weeks, mainline U-Boot will get support to generate the
bin_hdr with the DDR training code itself. By implementing this code
as SPL U-Boot. Then this file will not be needed any more and will
get removed.
Signed-off-by: Stefan Roese <sr@denx.de>
Actually, unmap_sysmem() does nothing. Just in case.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
- Do not insert a whitespace between a function name and
an open paranthesis
- Fix comment style
- Do not split an error message into multiple lines
even if it exceeds 80 columns
- Do not split "for" statement where it fits in 80 columns
- Do not use assignment in if condition
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Since commit fe1378a961 (ARM: use r9 for gd), r9 register
is used on ARM to hold global_data.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Jeroen Hofstee <jeroen@myspectrum.nl>
I finally had a look at the datasheet and spotted an additional
register address difference between regular E1000 and i210/i211 chips.
This patch fixes this and now successfully works on programmed
i210/i211 as well as unprogrammed i211.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
CONFIG_TPL should not be enabled for boards that do not have TPL.
CONFIG_SUPPORT_TPL introduced by this commit should be "select"ed
by boards with TPL support and CONFIG_TPL should depend on it.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
CONFIG_SPL should not be enabled for boards that do not have SPL.
CONFIG_SUPPORT_SPL introduced by this commit should be "select"ed
by boards with SPL support and CONFIG_SPL should depend on it.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
Commit 951860634f may have changed
the logic unintentially from "if (!(swfw_sync & (fwmask | swmask)))"
to "if ((swfw_sync & swmask) && !(swfw_sync & fwmask))". This change
breaks some e1000 NIC with a message "ERROR: Unable to read EEPROM!".
Signed-off-by: York Sun <yorksun@freescale.com>
CC: Marek Vasut <marex@denx.de>
CC: Tim Harvey <tharvey@gateworks.com>
Acked-by: Marcel Ziswiler <marcel@ziswiler.com>
CHUNK_TYPE_DONT_CARE should skip over the specified number of blocks, but
currently fails to increment the device block address. This results in
filesystem images getting written incorrectly. Add the missing block
address incrementing.
Cc: Steve Rae <srae@broadcom.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Steve Rae <srae@broadcom.com>
Enable EXT support in SPL for OMAP4 boards.
Build tested for duovero, omap4_sdp4430 and omap4_panda.
Run time tested on omap4_panda.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@ti.com>
Do not hang in spl_register_fat_device but return an error value.
It allows to use both CONFIG_SPL_FAT_SUPPORT and CONFIG_SPL_EXT_SUPPORT.
If FAT load fails, then EXT load is tried.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@ti.com>
Update documentation according to the EXT SPL support patch set.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Tom Rini <trini@ti.com>
Add EXT filesystem support to SPL.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
[trini: Fix a warning and checkpatch problems]
Signed-off-by: Tom Rini <trini@ti.com>
it is not correct to init for a specific slave in spi_setup_slave.
instead buffer the values and delay init until spi_claim_bus.
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
the second reset prevents other registers to be written.
This will prevent to have the correct signal levels for
SCLK before writing to the config reg in spi_xchg_single.
Tested with GPIO based chipselect and SPI_MODE_3 on i.MX6S
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Just move the configuration options scattered all over the driver
to the top of the source file. No functional change.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Add short documentation-alike note on how to use the Altera SPI
driver with the EPCS/EPCQx1 FPGA IP block on SoCFPGA Cyclone V
into doc/SPI/README.altera_spi
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
The variable d is used in rather questionable way. Rework the code
a bit so it's clearer what it does. Also, rename the variable from
d to data to make it's name less mysterious. Finally, change it's
data type to uint32_t , since it's accessed as a 32bit number.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
The driver contained an endless loop when waiting for TX completion,
this is a bad idea since if the hardware fails, the loop might spin
forever. Add timeout and handle it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
This patch just zaps most of the checkpatch cries present in the
driver. There is one more left, which will be addressed separately.
There is no functional change.
This patch also adds a bunch of newlines all around the place, this
is to make the code much more readable.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
