Commit Graph

7 Commits

Author SHA1 Message Date
Ben Warren
b24f119d67 Multi-bus I2C implementation of MPC834x
Hello,

Attached is a patch implementing multiple I2C buses on the MPC834x CPU
family and the MPC8349EMDS board in particular.
This patch requires Patch 1 (Add support for multiple I2C buses).
Testing was performed on a 533MHz board.

/*** Note: This patch replaces ticket DNX#2006083042000027 ***/

Signed-off-by: Ben Warren <bwarren@qstreams.com>

CHANGELOG:
        Implemented driver-level code to support two I2C buses on the
MPC834x CPU family and the MPC8349EMDS board.  Available I2C bus speeds
are 50kHz, 100kHz and 400kHz on each bus.

regards,
Ben
2006-11-03 19:42:19 -06:00
Wolfgang Denk
977b50f868 Minor cleanup. 2006-05-10 17:43:20 +02:00
Kumar Gala
8fe9bf61ef Merged MPC8349ADS and MPC8349EMDS ports into MPC8349EMDS port:
- Removed MPC8349ADS port
  - Added PCI support to MPC8349ADS
  - reworked memory map to allow mapping of all regions with BATs
  Patch by Kumar Gala 20 Apr 2006

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2006-04-20 13:45:32 -05:00
Wolfgang Denk
cf48eb9abd Some code cleanup 2006-04-16 10:51:58 +02:00
Rafal Jaworowski
dc9e499c62 Support for DDR with 32-data path. Addotional notes on injecting
multiple-bit errors.
2006-03-16 17:46:46 +01:00
Marian Balakowicz
d326f4a242 Add command for handling DDR ECC registers on MPC8349EE MDS board. 2006-03-16 15:19:35 +01:00
Marian Balakowicz
991425fe05 Add initial support for MPC8349E MDS board. 2006-03-14 16:24:38 +01:00