The Hammerhead platform is built around a AVR32 32-bit microcontroller
from Atmel. It offers versatile peripherals, such as ethernet, usb
device, usb host etc.
The board also incooperates a power supply and is a Power over Ethernet
(PoE) Powered Device (PD).
Additonally, a Cyclone III FPGA from Altera is integrated on the board.
The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two
DDR2 SDRAM interfaces, which will cover even the most exceptional need
of memory bandwidth. Together with the onboard video decoder the board
is ready for video processing.
For more information see: http:///www.miromico.com/hammerhead
Signed-off-by: Julien May <mailinglist@miromico.ch>
[haavard.skinnemoen@atmel.com: various small fixes and adaptions]
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
This moves the MMC and SD Card command definitions from
include/asm/arch/mmc.h into include/mmc.h. These definitions are
given by the MMC and SD Card standards, not by any particular
architecture.
There's a lot more room for consolidation in the MMC drivers which
I'm hoping to get done eventually, but this patch is a start.
Compile-tested for all avr32 boards as well as lpc2292sodimm and
lubbock. This should cover all three mmc drivers in the tree.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
This adds a driver for the SPI controller found on most AT91 and AVR32
chips, implementing the new SPI API.
Changed in v4:
- Update to new API
- Handle zero-length transfers appropriately. The user may send a
zero-length SPI transfer with SPI_XFER_END set in order to
deactivate the chip select after a series of transfers with chip
select active. This is useful e.g. when polling the status
register of DataFlash.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
This cleans up the SDRAM initialization and related code a bit, and
allows faster booting.
* Add definitions for EBI and internal SRAM to asm/arch/memory-map.h
* Remove memory test from sdram_init() and make caller responsible
for verifying the SDRAM and determining its size.
* Remove base_address member from struct sdram_config (was sdram_info)
* Add data_bits member to struct sdram_config and kill CFG_SDRAM_16BIT
* Add support for a common STK1000 hack: 16MB SDRAM instead of 8.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
pm_init() was always more about clock initialization than anything
else. Dealing with PLLs, clock gating and such is also inherently
SoC-specific, so move it into a SoC-specific directory.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Rework the HMATRIX configuration interface so that it becomes easier
to configure the HMATRIX for boards with special needs, and add new
parts.
The HMATRIX header file has been split into a general,
chip-independent part with register definitions, etc. and a
chip-specific part with SFR bitfield definitions and master/slave
identifiers.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
get_macb_pclk_rate() and get_macb_hclk_rate() should be available when
the chip has a MACB controller, not when it has a USART.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
The existing code assumes the SDRAM row refresh period should always
be 15.6 us. This is not always true, and indeed on the ATNGW100, the
refresh rate should really be 7.81 us.
Add a refresh_period member to struct sdram_info and initialize it
properly for both ATSTK1000 and ATNGW100. Out-of-tree boards will
panic() until the refresh_period member is updated properly.
Big thanks to Gerhard Berghofer for pointing out this issue.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Add a chip-features file providing definitions of the form
AT32AP700x_CHIP_HAS_<peripheral>
to indicate the availability of the given peripheral on the currently
selected chip.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
The SoC-specific code for all the AT32AP700x CPUs is practically
identical; the only difference is that some chips have less features
than others. By doing this rename, we can add support for the AP7000
derivatives simply by making some features conditional.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
