brain-hackers_pepepper-mirror/u-boot-brain
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2 Commits

Author SHA1 Message Date
Xiaoliang Yang
f85a8e8d1d armv7: LS1021a: enable i-cache in start.S 
Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and
ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First
stage of u-boot can run faster after that. There is a description
about skip lowlevel init in board/freescale/ls1021atwr/README.

Signed-off-by: Xiaoliang Yang <xiaoliang.yang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
 2016-10-06 09:55:08 -07:00
Wang Huan
c8a7d9dab0 arm: ls102xa: Add basic support for LS1021ATWR board 
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021ATWR board.
 One DDR controller
 DUART1 is used as the console

For the detail board information, please refer to README.

Signed-off-by: Chen Lu <chen.lu@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
 2014-09-08 10:30:35 -07:00