Commit Graph

7590 Commits

Author SHA1 Message Date
Masahiro Yamada
3c5b20f1b7 mpc8xx: remove ELPT860 board support
This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: The LEOX team <team@leox.org>
2015-01-05 12:08:51 -05:00
Masahiro Yamada
ceaf499b50 powerpc: manroland: remove uc100, uc101, mucmc52, hmi1001 support
These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefan Roese <sr@denx.de>
2015-01-05 12:08:51 -05:00
Masahiro Yamada
5d2a5ef712 mpc8xx: remove FPS{850, 860}L, NSCU, SM850, TK885D, virtlab2 support
These boards are still non-generic boards.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
2015-01-05 12:08:50 -05:00
Tom Rini
b4a0b4006f Merge branch 'master' of git://git.denx.de/u-boot-spi 2015-01-02 07:42:58 -05:00
Tom Rini
a74a4a86a5 Merge branch 'master' of git://git.denx.de/u-boot-tegra 2015-01-01 15:10:39 -05:00
Peng Fan
be2fde60b0 imx:mx6slevk add spi nor boot support
Add spi nor boot support for mx6slevk board.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-31 14:54:01 +05:30
Peng Fan
fad7d735a0 imx:mx6sxsabresd add qspi support
Configure the pad setting and enable qspi clock to support qspi
flashes access.

Add QSPI related macro in configuration header file.

Note:
mx6sxsabresd Revb board, 32M flash is used, but in header file,
CONFIG_SPI_FLASH_BAR is not defined, and we still use SZ_16M.
The LUT initialization qspi_set_lut function uses 32BIT addr,
however CONFIG_SPI_FLASH_BAR  and 24BIT addr should be used to
access bigger than 16MB size flash, and BRRD/BRWR should also
be supported. Future patches will fix this.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2014-12-31 14:52:32 +05:30
Tom Rini
5523cc2b8a Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-12-30 12:17:18 -05:00
Tom Rini
87b27c7aa7 Merge branch 'master' of git://git.denx.de/u-boot-samsung 2014-12-30 09:11:42 -05:00
Fabio Estevam
87e47e9058 mx6slevk: Remove get_board_rev()
get_board_rev() just returns the cpu revision, which does not make it really
useful for distinguishing between revisions of the board.

Let's get rid of get_board_rev() as it is not being used with its correct
meaning.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-12-30 14:10:39 +01:00
Marek Vasut
331ae846ad arm: mx6: novena: Add proper LVDS display support
Repair the register configuration and add proper support for the
display attached to both LVDS channels.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
2014-12-30 14:10:31 +01:00
Marek Vasut
f2e4d6a58c arm: mx6: novena: Pull video handling into separate file
Pull all of the video handling into a separate file, since a lot
more code will be added and such code would polute the board file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
2014-12-30 14:06:43 +01:00
Marek Vasut
d59d7b915e arm: mx6: novena: Pull GPIO definitions into header
Pull the definitions of GPIOs into a separate header file, so that
they can be used across all source files.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
2014-12-30 14:06:10 +01:00
Marek Vasut
998e121a2e arm: mx6: novena: Minor coding style fix
Just zap multiple spaces and replace them with tabs properly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
2014-12-30 14:05:56 +01:00
Stefano Babic
4e0114d967 Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
2014-12-30 13:04:38 +01:00
Stephen Warren
914627fe1c ARM: rpi: consolidate board rev error checking
Create a fake model table entry with default values, so we can error
check the board rev value once when querying it from the firmware, rather
than error-checking for invalid board rev values every time the model
table is used.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2014-12-29 16:31:22 -05:00
Stephen Warren
47705eff7a ARM: rpi: support model A+
Add a board rev entry for the new model A+, and augment the board
rev error handling code to be a bit more verbose.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2014-12-29 16:31:22 -05:00
Stephen Warren
3207d8fc9c ARM: rpi: only set usbethaddr on relevant systems
Model A and CM RPis don't have an on-board USB Ethernet device. Hence,
there's no point setting $usbethaddr based on the device fuses. Use the
model detection code to gate this. Note that the fuses are actually
programmed even on those devices though.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2014-12-29 16:31:22 -05:00
Linus Walleij
058235c06b vexpress64: take over maintenance of the semi vexpress64
As agreed with Steve Rae I'm taking over maintenance of the
semihosted, emulated FVP/foundation model Versatile Express
64 bit board variant.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Steve Rae <srae@broadcom.com>
2014-12-29 07:44:06 -05:00
Sjoerd Simons
68904c8322 ARM: exynos5420: Leave VBUS GPIO configuration up to common code
Since commit 4a271cb1b4 (exynos: usb: Switch USB VBUS GPIOs to be
device tree configured) it's not needed for the board specific files to
turn on the VBUS GPIO by hand as that gets done based on device tree. So
drop the redundant code from the SMDK5420 board file.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-22 20:49:41 +09:00
Sjoerd Simons
a7b99204a0 exynos5420: fix compilation without parade video
Not all exynos 5420 based devices with an LCD also have a parade LVDS
bridge. So make sure compilation doesn't break if CONFIG_LCD is enabled
and CONFIG_VIDEO_PARADE is not.

As a side-effect move the parade functions from the exynos system header
file to its own file.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-22 20:38:27 +09:00
Hyungwon Hwang
6207604f9c Odroid-XU3: Add support for Odroid-XU3
This patch adds support for Odroid-XU3.

Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Reviewed-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Tested-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-12-22 20:37:10 +09:00
Jan Luebbe
7ae350a030 arm: mxs: olinuxino: move DRAM config tuning to SPL
The weak mxs_adjust_memory_params function is called from spl_mem_init.c,
so it must be linked into the SPL to have an effect. Move it from
mx23_olinuxino.c to spl_boot.c.

This change was verified by reading back the register values.

Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2014-12-19 15:32:14 +01:00
Fabio Estevam
76494f7ac3 mx51evk: Fix MX51EVK_USB_CLK_EN_B definition
As per the mx51evk schematics MX51EVK_USB_CLK_EN_B is GPIO2_1, not GPIO2_2.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-12-19 15:32:14 +01:00
Stefan Roese
576cd6b3fa arm: mx6: gw_ventana: Change clock init to enable NAND related clocks
Otherwise NAND booting is likely to fail. Since this disables the NAND related
clocks and SPL can't load the main U-Boot from NAND.

This problem was introduced with this patch:

e25fbe3f (gw_ventana: Move the DCD settings to spl code)

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-12-19 15:32:14 +01:00
Peng Fan
fb00bda705 imx:mx6qarm2 add board level support for usb
Add pinmux settings and implement board_ehci_hcd_init

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2014-12-19 15:32:13 +01:00
Peng Fan
5a3d63c5cd imx:mx6sabresd add board level support for usb
Add pinmux settings, implement board_ehci_hcd_init and board_ehci_power

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2014-12-19 15:32:13 +01:00
Bin Meng
0ff65eb99c x86: crownbay: Enable Intel E1000 NIC support
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:07 -07:00
Bin Meng
58f542de30 x86: Add queensbay and crownbay Kconfig files
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Bin Meng
b71eec3129 x86: ich6-gpio: Add Intel Tunnel Creek GPIO support
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.

Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Bin Meng
b2e02d2865 x86: Add basic support to queensbay platform and crownbay board
Implement minimum required functions for the basic support to
queensbay platform and crownbay board.

Currently the implementation is to call fsp_init() in the car_init().
We may move that call to cpu_init_f() in the future.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-18 17:26:06 -07:00
Thierry Reding
6e2fca94ff ARM: tegra: Enable PCIe on Jetson TK1
The Jetson TK1 has an ethernet NIC connected to the PCIe bus and routes
the second root port to a miniPCIe slot. Enable the PCIe controller and
the network driver to allow the device to boot over the network.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
5a2c96a0e5 ARM: tegra: Enable PCIe on Cardhu
The PCIe bus on Cardhu is routed to the dock connector. An ethernet NIC
is available on the dock over the PCIe bus. Enable the PCIe controller
and the network device driver so that the device can boot over the
network.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:21 -07:00
Thierry Reding
7dd8738f08 ARM: tegra: Enable PCIe on TrimSlice
The TrimSlice has an ethernet NIC connected to the PCIe bus. Enable the
PCIe controller and the network driver so that the device can boot over
the network.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Thierry Reding
79c7a90f6c ARM: tegra: Implement XUSB pad controller
This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
with weak symbols on Tegra114.

Tegra20 and Tegra30 also provide weak symbols for these functions so
that drivers can use the same API irrespective of which SoC they're
being built for.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-12-18 13:19:20 -07:00
Tom Rini
e3bf81b1e8 Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx 2014-12-16 15:20:02 -05:00
Tom Rini
3bfbf32b6f Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2014-12-16 09:41:00 -05:00
Pavel Machek
065496d1b5 arm: socfpga: board: Repair Micrel PHY tuning
Add proper error checking into the PHY tuning patch. Make the PHY tunning only
happen in case the KSZ9021 PHY is enabled in config. Call the config callback
after the tuning finished.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Pavel Machek <pavel@denx.de>
2014-12-16 15:32:14 +01:00
Tang Yuantian
0023352855 mpc85xx/t104xrdb: convert deep sleep to generic board interface
A new interface is introduced to support generic board structure.
Converts it to use new interface.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-15 09:17:12 -08:00
Bin Meng
2795573a8c x86: ich6-gpio: Move setup_pch_gpios() to board support codes
Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:04 -07:00
Bin Meng
64542f4616 x86: Make ROM_SIZE configurable in Kconfig
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-13 22:32:03 -07:00
Tom Rini
a5a5882611 Merge git://git.denx.de/u-boot-dm 2014-12-11 20:47:34 -05:00
Tom Rini
fc9b0b8043 Merge branch 'master' of git://git.denx.de/u-boot-usb
Conflicts:
	board/freescale/mx6sxsabresd/mx6sxsabresd.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-12-11 18:40:49 -05:00
Tom Rini
2c49323d5d Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2014-12-11 18:28:09 -05:00
Simon Glass
b0e6ef4640 dm: i2c: tegra: Convert to driver model
This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:

   - CONFIG_SYS_I2C_INIT_BOARD
   - CONFIG_I2C_MULTI_BUS
   - CONFIG_SYS_MAX_I2C_BUS
   - CONFIG_SYS_I2C_SPEED
   - CONFIG_SYS_I2C

This has been tested on:
- trimslice (no I2C)
- beaver
- Jetson-TK1

It has not been tested on Tegra 114 as I don't have that board.

Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:44 -07:00
Allen Martin
a6c7b46181 ARM: tegra: Add support for nyan-big board
Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but
it has a different panel, the sdcard cd and wp sense are flipped, and it has
a different revision of the AS3722 PMIC.

This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD, NVIDIA
Tegra K1, 2GB). The display is not currently supported, so it should
boot on other nyan-based Chromebooks also, but only the device tree for
nyan-big is provided here.

The device tree file is from Linux but with features removed which are
unlikely to be supported in U-Boot soon (regulators, pinmux). Also the
addresses are updated to 32-bit.

Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
(rebase, change to 'nyan-big', fix pinmux that resets nyan-big)
2014-12-11 13:18:44 -07:00
Simon Glass
115066666c dm: rpi: Move serial to driver model
Adjust the configuration to use the driver model version of the pl01x
serial driver. Add the required platform data.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
2014-12-11 13:18:41 -07:00
Xiubo Li
660673af4f ARM: ls102xa: Setting device's stream id for SMMUs.
LS1 has 4 SMMUs for address translation of the masters. All the
SMMUs' stream IDs are 8-bit. The address translation depends on the
stream ID of the incoming transaction.
Each master has unique stream ID assigned to it and is configurable
through SCFG registers. The stream ID for the masters is identical
and share the same register field of STREAM ID registers.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:22 -08:00
Xiubo Li
e87f3b308c ARM: ls102xa: allow all the peripheral access permission as R/W.
The Central Security Unit (CSU) allows secure world software to
change the default access control policies of peripherals/bus
slaves, determining which bus masters may access them. This
allows peripherals to be separated into distinct security domains.
Combined with SMMU configuration of the system masters privileges,
these features provide protection against indirect unauthorized
access to data.

For now we configure all the peripheral access permissions as R/W.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:12 -08:00
Tang Yuantian
a7787b7850 fsl/sleep: updated the deep sleep framework for QorIQ platforms
With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:18 -08:00