3 Commits

Author	SHA1	Message	Date
Weijie Gao	2dca3cc2a9	clk: MediaTek: bind ethsys reset controller ... The ethsys contains not only the clock gating controller, but also the reset controller for the whole ethernet subsystem and its components. This patch adds binding of the reset controller so that the ethernet node can have references on it. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>	2019-01-14 17:43:18 -05:00
Ryder Lee	c746651550	clk: MediaTek: add clock driver for MT7623 SoC. ... This patch adds a driver for MT7623 clock blocks. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>	2018-11-28 23:04:51 -05:00
Ryder Lee	0bd7dc74d2	clk: MediaTek: add clock driver for MT7629 SoC. ... This patch adds clock modules for MediaTek SoCs: - Shared part: a common driver which contains the general operations for plls, muxes, dividers and gates so that we can reuse it in future. - Specific SoC part: the group of structures used to hold the hardware configuration for each SoC. We take MT7629 as an example to demonstrate how to implement driver if any other MediaTek chips would like to use it. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>	2018-11-28 23:04:51 -05:00