3 Commits

Author	SHA1	Message	Date
York Sun	207774b213	armv8/ls2085a: Fix generic timer clock source ... The timer clock is system clock divided by 4, not fixed 12MHz. This is common to the SoC, not board specific. Primary core is fixed when u-boot still runs in board_f. Secondary cores are fixed by reading a variable set by u-boot. Signed-off-by: York Sun <yorksun@freescale.com> CC: Mark Rutland <mark.rutland@arm.com>	2015-04-23 08:55:55 -07:00
Arnab Basu	60385d94e5	ARMv8/fsl-lsch3: Patch cpu node properties in DT for online cores ... U-Boot should only add "enable-method" and "cpu-release-address" properties to the "cpu" node of the online cores. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>	2015-02-24 13:08:28 -08:00
York Sun	40f8dec54d	armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page ... Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>	2014-09-25 08:36:19 -07:00