Commit Graph

5 Commits

Author SHA1 Message Date
Priyanka Jain
39c2a6eb75 p1_p2_rdb: to set SQW/INT pin of RTC as INT line
SQW/INT pin in RTC can be used for generating square wave(by default) or
as interrupt line.  U-boot is registering this pin for interrupts.
Configuring SQW/INT bit as interrupt line during board initialization
to avoid spurious interrupts generated by square wave.

Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-11-12 09:45:11 -06:00
Poonam Aggrwal
75997dc54f 85xx/p1_p2_rdb: Added RevD board version support
- Also modified the code to use io accessors.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
2010-06-29 21:07:26 +02:00
Kumar Gala
1749c3da8d ppc/85xx: Fixup PCI nodes for P1_P2_RDB
While we had ft_pci_board_setup it wasn't being called by
ft_board_setup.  Fix that so we actually update the device tree PCI
nodes on P1_P2_RDB boards.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-04-26 22:37:50 -05:00
Kumar Gala
5fb6ea3ad3 ppc/85xx: Make flash TLB entry determined at runtime on FSL boards
Rather than hard coding which TLB entry the FLASH is mapped with we can
use find_tlb_idx to determine the entry.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-01-05 13:49:08 -06:00
Poonam Aggrwal
728ece343e 85xx: Add support for P2020RDB board
The code base adds P1 & P2 RDB platforms support.
The folder and file names can cater to future SOCs of P1/P2 family.
P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series.

Tested following on P2020RDB:
1. eTSECs
2. DDR, NAND, NOR, I2C.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:38 -05:00